DS2154L vs. DS2153Q
abstract: this application note highlights the differences between the ds2154l and the ds2153q e1 single chip transceivers (scts). the ds2154l is a superset of the ds2153q. all of the original features of the ds2153q have been retained and software created for the ds2153q is transferable to the ds2154l with minimal effort. when implementing the new features of the ds2154l, a priority was placed on preserving the ds2153q's register map to facilitate code migration from existing ds2153q designs. this note highlights register additions and differences found in the ds2154l. this note also highlights specific registers containing bit locations related to new features.
1.0 introductionthis application note highlights the differences between the ds2154l and the ds2153q e1 single chip transceivers. the ds2154l is a superset of the ds2153q. all of the original features of the ds2153q have been retained and software created for the ds2153q is transferable to the ds2154l with minimal effort.
2.0 additional functionality option for non-multiplexed bus operation crystal-less jitter attenuation additional hardware signaling capability
receive signaling reinsertion to a backplane multiframe sync
availability of signaling in a separate pcm data stream
signaling freezing
interrupt generated on change of signaling data improved receive sensitivity: 0db to -43db per-channel code insertion in both transmit and receive paths expanded access to sa and si bits rcl, rlos, rra, and rais alarms now interrupt on change of state 8.192mhz clock synthesizer per-channel loopback capability addition of hardware pins to indicate carrier loss and signaling freeze line interface function can be completely decoupled from the framer/formatter to allow:
interface to optical, hdsl, and other nrz interfaces
be able to tap the transmit and receive bipolar data streams for monitoring purposes
be able to corrupt data and insert framing errors, crc errors, etc. transmit and receive elastic stores now have independent backplane clocks ability to monitor ds0 channel in both the transmit and receive paths access to the data stream in between the framer/formatter and the elastic stores ais generation in the line interface that is independent of loopbacks transmit current limiter to meet the 50ma short circuit requirement option to extend carrier loss criteria to a 1 ms period as per ets 300 233 automatic rai generation to ets 300 011 specifications device identification register 3.0 changes in register definitionswhen implementing the new features of the ds2154l, a priority was placed on preserving the ds2153qs register map to facilitate code migration from existing ds2153q designs. this section highlights register additions and differences found in the ds2154l.
3.1 new feature register usagehighlights specific registers containing bit locations related to new features. each item can be found in the data sheet under the listed sections.
3.1.1 ds0 monitoring (section 6.0)
register description
ccr4 common control 4 (bits 4 - 0)
ccr5 common control 5 (bits 4 - 0)
tds0m transmit ds0 monitor
rds0m receive ds0 monitor
3.1.2 hardware based signaling (section 7.2)
register description
ts1-ts16 transmit signaling registers 1 - 16
tcbr1-4 transmit channel blocking registers 1 - 4
tcr1 transmit control register 1
ccr3 common control 3 (bits 3 and 2)
3.1.3 signaling freeze (section 3.0 and 7.2)
register description
ccr2 common control 2 (bits 1 and 0)
3.1.4 per channel loopback (section 8.1.1)
register description
ccr3 common control 3 (bit 5)
tir1 - tir4 transmit idle registers 1 - 4
3.1.5 per channel code (idle) insertion (section 8.0)
register description
tcc1 - tcc4 transmit channel control 1 - 4
tc1 - tc32 transmit channels registers 1 - 32
rcc1 - rcc4 receive channel control 1 - 4
rc1 - rc32 receive channels registers 1 - 32
3.1.6 device identification (section 3.0)
register description
idr device identification
3.1.7 interrupt on change of state for rcl, rlos, rra, rais (section 4.0)
register description
sr1 status register 1 (bits 7 and 5)
imr1 interrupt mask register 1 (bits 7 and 5)
3.1.8 receive carrier loss alternate criteria (section 3.0)
register description
ccr3 common control 3 (bit 0)
3.1.9 expanded access to sa and si bits (section 11.0)
register description
sr2 status register 2 (bit 1)
rsiaf receive si bits in the align frame
rsinaf receive si bits in the non-align frame
rra receive remote alarm
rsa4 - rsa8 receive sa bits
tsacr transmit sa bit control register
tsiaf transmit si bits in the align frame
tsinaf transmit si bits in the non-align frame
tra transmit remote alarm
tsa4 - tsa8 transmit sa bits
3.2 bit assignment changes within existing registers
highlights bit locations in the ds2154l which have changed from the ds2153q. register bit # ds2153q
symbol b>ds2153q
description ds2154l
symbol ds2151l
description
rcr2 2 rsclkm receive side sysclk mode select rbcs receive side backplane clock select
tcr1 7 n/a not assigned odf output data format
tcr2 2 n/a not assigned odm output data mode
ccr2 1 rlb remote loop back rff receive force freeze
ccr2 0 llb local loop back rfe receive freeze enable
ccr3 3 lirst line interface reset rsre receive side signaling re-insertion enable
ccr3 2 n/a not assigned tsre transmit side signaling re-insertion enable
ccr3 1 tsclkm transmit side sysclk mode select tbcs transmit side backplan clock select
ccr3 0 n/a not assigned rcla receive carrier loss (rcl) alternate criteria
3.3 register bit moves
function/td> ds2153q location sd2154l location
lirst ccr3.3 ccr5.7
llb ccr2.0 ccr4.6
rlb ccr2.1 ccr4.7
4.0 changes in device pin out 4.1 package typesthe ds2154l is offered in a 100 pin 14mm x 14mm x 1.4mm lqfp. the ds2153q is offered in a 44 pin 16.7mm x 16.7mm x 4.0mm plcc. values listed are for body dimensions.
4.2 device pin differences4.2.1 control pot pins
ds2154l ds2153q description
int1 int1, int2 flags host controller during conditions and change of conditions in the status registers 1 and 2, and the fdl status register
test n/a device pin tri-state enable
mux n/a multiplexed/non-multiplexed bus operation select
d0:d7 or ad0:ad7 ad0:ad7 multiplexed/non-multiplexed bus
a0:a6 n/a address bus
a7 or ale ale a7 in non-multiplexed bus operation, ale in multiplexed bus operation
4.2.2 line interface pins
ds2154l ds2153q description
mclk n/a a 2.048mhz ttl clock input used for clock/data recovery and for jitter attenuation.
mclk, xtald xtal1, xtal2 2.048mhz quartz crystal option instead of a ttl level clock at mclk.
8xclk n/a an 8 x 2.048mhz clock that is frequency locked to either the clock/data recovery block or the tclki pin.
liuc n/a line interface circuitry connect enable.
rposo n/a receive line interface rpos bipolar data output.
rnego n/a receive line interface rneg bipolar data output
rclko n/a buffered recovered clock from the e1 line.
tposi n/a transmit line interface tpos data input.
tnegi n/a transmit line interface tneg data input.
tclki n/a transmit line interface clock input.
4.2.3 transmit side digital pins
ds2154l ds2153q description
tsysclk n/a transmit side elastic store clock.
tssync n/a transmit side elastic store frame or multiframe sync input.
tsig n/a outgoing signaling data input.
teso n/a transmit elastic store data output.
tdata n/a transmit formatter data input.
tposo n/a transmit formatter tpos data output.
tnego n/a transmit formatter tneg data output.
tclko n/a buffered clock used to move data through the transmit side formatter.
4.2.4 receive side digital pins
ds2154l ds2153q description
rfsync n/a receive frame sync.
rmsync n/a receive multiframe sync.
rdata n/a receive side framer data output.
rsysclk n/a receive side elastic store clock.
rsig n/a receive signaling bits output.
rcl n/a receive carrier loss indication.
rsigf n/a receive signaling freeze indication.
8mclk n/a 8.192mhz clock referenced to rclk.
rposi n/a receive side framer positive data input.
rnegi n/a receive side framer negative data input.
rclki n/a receive side framer clock input.
视觉系统技术在贴片机中的原理及作用
数码通在香港推出5G服务，爱立信快速推出先进服务并高效运营
lg34uc97评测 各方面都达到专业级别
在工业互联网这个领域,中国距离世界第一还有多远的距离?
防疫机器人在防疫领域的应用：红外测温，口罩识别
DS2154L vs. DS2153Q
汽车电子产品的爆发式发展持续推动连接器市场的强劲增长
美国国家半导体推出业界最低抖动的3Gbps SDI均衡器
第三代无线通信标准
一个老工程师给新毕业大学生的几点建议
冬季保养空调室内外三步曲
电力变压器的工作原理
晶体管和二极管为什么会有那么多品种？
瑞萨电子收购Sequas交易获得CFIUS批准
M圈在实际装配中的应用
TE推出新一代Grace Inertia连接器GI 2.5和GI 3.3
1452双输出霍尔开关是一款可替代迈来芯MLX92251的双霍尔集成电路
浦桑尼克扫地机器人LDSD550评测 采用方形设计清扫更加聪明高效
Cadence宣布提供业界首款HDMI 2.0验证IP
主流芯片厂商纷纷抢跑5G芯片，联发科成为5G芯片市场的巨大新变量
1.0 introductionthis application note highlights the differences between the ds2154l and the ds2153q e1 single chip transceivers. the ds2154l is a superset of the ds2153q. all of the original features of the ds2153q have been retained and software created for the ds2153q is transferable to the ds2154l with minimal effort.
2.0 additional functionality option for non-multiplexed bus operation crystal-less jitter attenuation additional hardware signaling capability
receive signaling reinsertion to a backplane multiframe sync
availability of signaling in a separate pcm data stream
signaling freezing
interrupt generated on change of signaling data improved receive sensitivity: 0db to -43db per-channel code insertion in both transmit and receive paths expanded access to sa and si bits rcl, rlos, rra, and rais alarms now interrupt on change of state 8.192mhz clock synthesizer per-channel loopback capability addition of hardware pins to indicate carrier loss and signaling freeze line interface function can be completely decoupled from the framer/formatter to allow:
interface to optical, hdsl, and other nrz interfaces
be able to tap the transmit and receive bipolar data streams for monitoring purposes
be able to corrupt data and insert framing errors, crc errors, etc. transmit and receive elastic stores now have independent backplane clocks ability to monitor ds0 channel in both the transmit and receive paths access to the data stream in between the framer/formatter and the elastic stores ais generation in the line interface that is independent of loopbacks transmit current limiter to meet the 50ma short circuit requirement option to extend carrier loss criteria to a 1 ms period as per ets 300 233 automatic rai generation to ets 300 011 specifications device identification register 3.0 changes in register definitionswhen implementing the new features of the ds2154l, a priority was placed on preserving the ds2153qs register map to facilitate code migration from existing ds2153q designs. this section highlights register additions and differences found in the ds2154l.
3.1 new feature register usagehighlights specific registers containing bit locations related to new features. each item can be found in the data sheet under the listed sections.
3.1.1 ds0 monitoring (section 6.0)
register description
ccr4 common control 4 (bits 4 - 0)
ccr5 common control 5 (bits 4 - 0)
tds0m transmit ds0 monitor
rds0m receive ds0 monitor
3.1.2 hardware based signaling (section 7.2)
register description
ts1-ts16 transmit signaling registers 1 - 16
tcbr1-4 transmit channel blocking registers 1 - 4
tcr1 transmit control register 1
ccr3 common control 3 (bits 3 and 2)
3.1.3 signaling freeze (section 3.0 and 7.2)
register description
ccr2 common control 2 (bits 1 and 0)
3.1.4 per channel loopback (section 8.1.1)
register description
ccr3 common control 3 (bit 5)
tir1 - tir4 transmit idle registers 1 - 4
3.1.5 per channel code (idle) insertion (section 8.0)
register description
tcc1 - tcc4 transmit channel control 1 - 4
tc1 - tc32 transmit channels registers 1 - 32
rcc1 - rcc4 receive channel control 1 - 4
rc1 - rc32 receive channels registers 1 - 32
3.1.6 device identification (section 3.0)
register description
idr device identification
3.1.7 interrupt on change of state for rcl, rlos, rra, rais (section 4.0)
register description
sr1 status register 1 (bits 7 and 5)
imr1 interrupt mask register 1 (bits 7 and 5)
3.1.8 receive carrier loss alternate criteria (section 3.0)
register description
ccr3 common control 3 (bit 0)
3.1.9 expanded access to sa and si bits (section 11.0)
register description
sr2 status register 2 (bit 1)
rsiaf receive si bits in the align frame
rsinaf receive si bits in the non-align frame
rra receive remote alarm
rsa4 - rsa8 receive sa bits
tsacr transmit sa bit control register
tsiaf transmit si bits in the align frame
tsinaf transmit si bits in the non-align frame
tra transmit remote alarm
tsa4 - tsa8 transmit sa bits
3.2 bit assignment changes within existing registers
highlights bit locations in the ds2154l which have changed from the ds2153q. register bit # ds2153q
symbol b>ds2153q
description ds2154l
symbol ds2151l
description
rcr2 2 rsclkm receive side sysclk mode select rbcs receive side backplane clock select
tcr1 7 n/a not assigned odf output data format
tcr2 2 n/a not assigned odm output data mode
ccr2 1 rlb remote loop back rff receive force freeze
ccr2 0 llb local loop back rfe receive freeze enable
ccr3 3 lirst line interface reset rsre receive side signaling re-insertion enable
ccr3 2 n/a not assigned tsre transmit side signaling re-insertion enable
ccr3 1 tsclkm transmit side sysclk mode select tbcs transmit side backplan clock select
ccr3 0 n/a not assigned rcla receive carrier loss (rcl) alternate criteria
3.3 register bit moves
function/td> ds2153q location sd2154l location
lirst ccr3.3 ccr5.7
llb ccr2.0 ccr4.6
rlb ccr2.1 ccr4.7
4.0 changes in device pin out 4.1 package typesthe ds2154l is offered in a 100 pin 14mm x 14mm x 1.4mm lqfp. the ds2153q is offered in a 44 pin 16.7mm x 16.7mm x 4.0mm plcc. values listed are for body dimensions.
4.2 device pin differences4.2.1 control pot pins
ds2154l ds2153q description
int1 int1, int2 flags host controller during conditions and change of conditions in the status registers 1 and 2, and the fdl status register
test n/a device pin tri-state enable
mux n/a multiplexed/non-multiplexed bus operation select
d0:d7 or ad0:ad7 ad0:ad7 multiplexed/non-multiplexed bus
a0:a6 n/a address bus
a7 or ale ale a7 in non-multiplexed bus operation, ale in multiplexed bus operation
4.2.2 line interface pins
ds2154l ds2153q description
mclk n/a a 2.048mhz ttl clock input used for clock/data recovery and for jitter attenuation.
mclk, xtald xtal1, xtal2 2.048mhz quartz crystal option instead of a ttl level clock at mclk.
8xclk n/a an 8 x 2.048mhz clock that is frequency locked to either the clock/data recovery block or the tclki pin.
liuc n/a line interface circuitry connect enable.
rposo n/a receive line interface rpos bipolar data output.
rnego n/a receive line interface rneg bipolar data output
rclko n/a buffered recovered clock from the e1 line.
tposi n/a transmit line interface tpos data input.
tnegi n/a transmit line interface tneg data input.
tclki n/a transmit line interface clock input.
4.2.3 transmit side digital pins
ds2154l ds2153q description
tsysclk n/a transmit side elastic store clock.
tssync n/a transmit side elastic store frame or multiframe sync input.
tsig n/a outgoing signaling data input.
teso n/a transmit elastic store data output.
tdata n/a transmit formatter data input.
tposo n/a transmit formatter tpos data output.
tnego n/a transmit formatter tneg data output.
tclko n/a buffered clock used to move data through the transmit side formatter.
4.2.4 receive side digital pins
ds2154l ds2153q description
rfsync n/a receive frame sync.
rmsync n/a receive multiframe sync.
rdata n/a receive side framer data output.
rsysclk n/a receive side elastic store clock.
rsig n/a receive signaling bits output.
rcl n/a receive carrier loss indication.
rsigf n/a receive signaling freeze indication.
8mclk n/a 8.192mhz clock referenced to rclk.
rposi n/a receive side framer positive data input.
rnegi n/a receive side framer negative data input.
rclki n/a receive side framer clock input.
视觉系统技术在贴片机中的原理及作用
数码通在香港推出5G服务，爱立信快速推出先进服务并高效运营
lg34uc97评测 各方面都达到专业级别
在工业互联网这个领域,中国距离世界第一还有多远的距离?
防疫机器人在防疫领域的应用：红外测温，口罩识别
DS2154L vs. DS2153Q
汽车电子产品的爆发式发展持续推动连接器市场的强劲增长
美国国家半导体推出业界最低抖动的3Gbps SDI均衡器
第三代无线通信标准
一个老工程师给新毕业大学生的几点建议
冬季保养空调室内外三步曲
电力变压器的工作原理
晶体管和二极管为什么会有那么多品种？
瑞萨电子收购Sequas交易获得CFIUS批准
M圈在实际装配中的应用
TE推出新一代Grace Inertia连接器GI 2.5和GI 3.3
1452双输出霍尔开关是一款可替代迈来芯MLX92251的双霍尔集成电路
浦桑尼克扫地机器人LDSD550评测 采用方形设计清扫更加聪明高效
Cadence宣布提供业界首款HDMI 2.0验证IP
主流芯片厂商纷纷抢跑5G芯片，联发科成为5G芯片市场的巨大新变量