RT9173D应用电路及参数资料
rt9173d应用电路及参数资料
cost-effective, peak 3a sink/source bus termination regulator
the rt9173d is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the jedec sstl_2 and sstl_18 or other specific interfaces such as hstl, scsi-2 and scsi-3 etc. devices requirements. the regulator is capable of actively sinking or sourcing continuous 2a or up to 3a transient peak current while regulating an output voltage to within 40mv. the output termination voltage cab be tightly regulated to track 1/2vddq by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the refen pin voltage.
the rt9173d also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection.
the rt9173d are available in the sop-8 (exposed pad) surface mount packages.
features
• ideal for ddr-i, ddr-ii and ddr-iii vtt applications
• sink and source current
► 2a continuous current
► peak 3a for ddri and ddrii
► peak 2.5a for ddriii
• integrated power mosfets
• generates termination voltage for sstl_2, sstl _18, hstl, scsi-2 and scsi-3 interfaces
• high accuracy output voltage at full-load
• output adjustment by two external resistors
• low external component count
• shutdown for suspend to ram (str) functionality with high-impedance output
• current limiting protection
• on-chip thermal protection
• available in sop-8 (exposed pad) packages
• vin and vcntl no power sequence issue
• rohs compliant and 100% lead (pb)-free
application
• desktop pcs, notebooks, and workstations
• graphics card memory termination
• set top boxes, digital tvs, printers
• embedded systems
• active termination buses
• ddr-i, ddr-ii and ddr-iii memory systems
typical applications circuit
r1 = r2 = 100kw, rtt = 50w / 33w / 25w
cout(min) = 10mf (ceramic) + 1000mf under the worst case testing condition
css = 1mf, cin = 470mf (low esr), ccntl = 47mf
rt9173d pdf datasheet
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RT9173D应用电路及参数资料
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cost-effective, peak 3a sink/source bus termination regulator
the rt9173d is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the jedec sstl_2 and sstl_18 or other specific interfaces such as hstl, scsi-2 and scsi-3 etc. devices requirements. the regulator is capable of actively sinking or sourcing continuous 2a or up to 3a transient peak current while regulating an output voltage to within 40mv. the output termination voltage cab be tightly regulated to track 1/2vddq by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the refen pin voltage.
the rt9173d also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection.
the rt9173d are available in the sop-8 (exposed pad) surface mount packages.
features
• ideal for ddr-i, ddr-ii and ddr-iii vtt applications
• sink and source current
► 2a continuous current
► peak 3a for ddri and ddrii
► peak 2.5a for ddriii
• integrated power mosfets
• generates termination voltage for sstl_2, sstl _18, hstl, scsi-2 and scsi-3 interfaces
• high accuracy output voltage at full-load
• output adjustment by two external resistors
• low external component count
• shutdown for suspend to ram (str) functionality with high-impedance output
• current limiting protection
• on-chip thermal protection
• available in sop-8 (exposed pad) packages
• vin and vcntl no power sequence issue
• rohs compliant and 100% lead (pb)-free
application
• desktop pcs, notebooks, and workstations
• graphics card memory termination
• set top boxes, digital tvs, printers
• embedded systems
• active termination buses
• ddr-i, ddr-ii and ddr-iii memory systems
typical applications circuit
r1 = r2 = 100kw, rtt = 50w / 33w / 25w
cout(min) = 10mf (ceramic) + 1000mf under the worst case testing condition
css = 1mf, cin = 470mf (low esr), ccntl = 47mf
rt9173d pdf datasheet
rfid天线有哪一些重要参数
智能继电器模块的作用与安装
等效电阻是什么意思
新一代印制电路板的核心技术是什么？
!!销售/收购! HP8657B HP8657B 信号源 H
RT9173D应用电路及参数资料
讯飞扫描词典笔获ZOL年度推荐产品奖：英语学习烦恼，一笔横扫
Home键消失，面容ID将至_iPad Pro该如何进行人机交互
GD32开发实战指南(基础篇) 第4章 GD32启动流程详解(Keil版)
洗浆机轴封位磨损原因及修复方法
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随着人工智能的快速发展会给我们带来什么影响
美国对华为的制裁造成了整个欧洲5G投资的延迟
深度解析华为“很吓人的技术”：GPU Turbo
Wi-Fi网络可以成为大学里一个强大的联系追踪工具
智慧酒店有人工智能的加入会有什么效果
数据规模拓展无极限，2023亚马逊云科技re:Invent大会首日精彩内容
油电混合无人机在救灾领域起到的重要作用
智慧城市是变革的主要机遇
“安卓之父”创业失败 主要原因是他没有找对智能手机的发展方向