技术简介40 ：了解可编程延迟线：概述DS1020，DS10
abstract: this is an earlier application note discussing the characteristics and capabilities of the ds1020, ds1021, and ds1045 programmable delay lines from dallas semiconductor. it discusses the architecture and functionality of the two programmable delay line families: the single delay ds1020/ds1021/ds1023 and the dual delay line ds1045. delay characteristics required by the design engineer such as linearity and effects of temperature are also discussed.
introductionthe system timing and control family includes programmable delay lines. these devices offer the user the ability to program the required delay after installation in the application rather than use factory-trimmed fixed-delay intervals. economic considerations usually dictate that this approach is used whenever dynamic delay adjustment is needed in the system, rather than as a convenience to avoid specifying particular fixed delay values.
figure 1.
ds1020/ds1021/ds1023 8-bit programmable silicon delay linesthese devices can be used in many of the same configurations illustrated here when dynamic alteration of system parameters is needed. the ds1020, ds1021, and ds1023 offer both parallel and serial methods of programming. in the parallel mode, an eight-bit word applied directly to a multiplexer, which selects the delay time desired. these values may also be set via a three-wire serial bus.
the ds1020 is a single 8-bit programmable delay line with a choice of serial or parallel programming. step sizes of 0.15ns, 0.25ns, 0.5ns, 1ns, and 2ns are available. the ds1021 is a similar, but lower-cost, device. it is offered only in so packaging, with step sizes of 0.25ns or 0.5ns only. the ds1023 is a more fully-featured device than the ds1020 and ds1021. it has a inherent step zero delay time of 16.5ns, with steps sizes of 0.25ns , 0.5ns ,1ns, 2ns, and 5ns. in addition to the standard features, it includes a step-one reference delay output, a pulse-width modulator output option, and an inverted output option. it is constructed using a different topology that allows delay times greater than the pulse width.
ds1045 4-bit dual programmable delay linethe ds1045 is effectively a 4-bit programmable delay line with two simultaneous programmable outputs from a single input. this device is particularly useful for skew adjustments as it allows either output to lead or lag the other.
figure 2.
internally, it is equivalent to a 16-tap delay line with two multiplexers for selecting which taps are routed to the outputs. each multiplexer has a 4-bit parallel input to select the required tap, so one byte of data could fully program the device.
in addition to the data sheet, there is additional characterization of this device in application note 421, device characteristics of the ds1045 dual 4-bit programmable delay line.
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introductionthe system timing and control family includes programmable delay lines. these devices offer the user the ability to program the required delay after installation in the application rather than use factory-trimmed fixed-delay intervals. economic considerations usually dictate that this approach is used whenever dynamic delay adjustment is needed in the system, rather than as a convenience to avoid specifying particular fixed delay values.
figure 1.
ds1020/ds1021/ds1023 8-bit programmable silicon delay linesthese devices can be used in many of the same configurations illustrated here when dynamic alteration of system parameters is needed. the ds1020, ds1021, and ds1023 offer both parallel and serial methods of programming. in the parallel mode, an eight-bit word applied directly to a multiplexer, which selects the delay time desired. these values may also be set via a three-wire serial bus.
the ds1020 is a single 8-bit programmable delay line with a choice of serial or parallel programming. step sizes of 0.15ns, 0.25ns, 0.5ns, 1ns, and 2ns are available. the ds1021 is a similar, but lower-cost, device. it is offered only in so packaging, with step sizes of 0.25ns or 0.5ns only. the ds1023 is a more fully-featured device than the ds1020 and ds1021. it has a inherent step zero delay time of 16.5ns, with steps sizes of 0.25ns , 0.5ns ,1ns, 2ns, and 5ns. in addition to the standard features, it includes a step-one reference delay output, a pulse-width modulator output option, and an inverted output option. it is constructed using a different topology that allows delay times greater than the pulse width.
ds1045 4-bit dual programmable delay linethe ds1045 is effectively a 4-bit programmable delay line with two simultaneous programmable outputs from a single input. this device is particularly useful for skew adjustments as it allows either output to lead or lag the other.
figure 2.
internally, it is equivalent to a 16-tap delay line with two multiplexers for selecting which taps are routed to the outputs. each multiplexer has a 4-bit parallel input to select the required tap, so one byte of data could fully program the device.
in addition to the data sheet, there is additional characterization of this device in application note 421, device characteristics of the ds1045 dual 4-bit programmable delay line.
华为P10国行版明日发布：价格是最大看点！
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联想推出ThinkServer SE550边缘服务器，助力企业智能化转型
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