Level Translators For SPI and
abstract: a serial interface is often used for board-level communication between different integrated circuits, especially in space-constrained applications at low-to medium data-rates. the most popular serial interfaces are i²c and spi™. if a system has different supply voltages for the µp and for peripheral devices, suitable level translators are required to be able to use one of these serial interfaces. there are several reasons why today? systems have two or more supply-voltages. high-speed µps and dsps are implemented on the most advanced processes to get maximum performance with the lowest power consumption. another reason for different supply voltages is the use of asics or fpgas together with a µp. for all these applications the designer needs a uni-or bi-directional level translator for the bus signals. the max3372e-max3379e/max3390e-max3393e family of level translators was designed to solve these problems.
a serial interface is often used for board-level communication between different integrated circuits, especially in space-constrained applications at low-to medium data-rates. the most popular serial interfaces are i²c and spi™.
this application note describes i²c and spi and some level-translation circuits that interface to them.
the spi-bus has 4 signals: active-low cs = active-low chip select, sclk = clock, din = data in, and dout = data out.
figure 1 illustrates the timing of these signals. the spi-specification has a clock polarity (cpol) and a clock phase (cpha) bit. figure 1 relates to the most common combination of these bits, cpol = 0 (data-transfer on the rising clock edge) and cpha = 0 (clock transitions in the middle of bit timing).
figure 1. signals and timing of the spi-interface.
several devices might be connected to the same bus, where all devices share the din and sclk-line. each device has a separate chip-select signal, so that the µp can address the appropriate part by the relevant active-low cs signal. if a chip does not talk back to the µp (e.g., dac), the dout-line is not needed. the spi-bus is well suited to data-rates to 20mbps. some devices (e.g., rtcs like the max6901) have a 3-wire interface, where the data-line is bi-directional. this interface is similar to spi.
the i²c-bus has 2 signals: scl = clock and sda = data in/out.
figure 2 illustrates the timing of the i²c-bus. each device has a unique 7-bit or 10-bit address. as the data-line is bi-directional, only 2 wires are required, which is an advantage in space-constrained applications or in designs where different parts of the circuit have to be optically isolated. data-rates for the i²c-bus are 100kbps, 400kbps, or even µp to 3.4mbps for the high-speed mode. the i²c-bus requires pull-up resistors rp, where the value of rp depends on the supply-voltage and the bus-capacitance (number of devices connected to the bus and length of the bus).
figure 2. signals and timing of the i²c-interface.
if a system has different supply voltages for the µp and for peripheral devices, suitable level translators are required to be able to use one of these serial interfaces. there are several reasons why today's systems have two or more supply-voltages. high-speed µps and dsps are implemented on the most advanced processes to get maximum performance with the lowest power consumption. these processes are often limited to supply voltages of 3v or less. typical core-voltages are 1.5v-2.5v. on the other hand, i/o-devices like da-and ad-converters might have a supply-voltage of 3.3v or 5v to achieve the required dynamic range. in portable and low-power applications there is another reason to have the µp run with the lowest possible supply voltage. current consumption of a typical microprocessor depends on clock frequency and supply voltage. one way to achieve low current consumption is therefore to reduce the supply voltage. this also leads to the situation where the µp runs from a different supply than other devices. another reason for different supply voltages might be the use of asics or fpgas together with a µp. for all these applications the designer needs a uni-or bi-directional level translator for the bus signals.
figure 3 shows a basic level translator with an n-channel mosfet. if neither q2 or q3 pulls the data-line low, vgs of q1 is 0v and data 1.8 has a level of 1.8v, data 3.3 is at 3.3v. if q2 pulls data 1.8 low, vgs of q1 is 1.8v and will turn on q1, pulling data 3.3 low. if q3 pulls data 3.3 low, the body diode of q1 will be forward-biased, pulling the source to 0.3v. vgs will be 1.5v and q1 will turn on, pulling data 1.8 low. so logic-levels are translated in both directions. we assume here that q2 has zero on-resistance. for a real application we would have to consider this on-resistance, which is 133ω worst-case for an i²c-compatible output (0.4v at 3ma) or 22ω for the 74lvc125 buffer (0.55v at 24ma). in this case the voltage vgs to turn on q1 would no longer be 1.8v, but would be lower, depending on r1 and the on-resistance of q1.
figure 3. basic level translator.
there are several problems associated with this circuit:
with vl being 1.8v or even lower, the choice of suitable mosfets with a low enough vgs threshold voltage is rather limited. one candidate might be the tn2501 from supertex. the slew-rate and, therefore, the maximum transmission rate depends on the value of r1/r2 and on the number of devices on the bus, which determines the capacitance. it is possible to increase the maximum transmission rate by choosing lower value resistors r1/r2. this will lead to higher current consumption, which is undesirable in portable/low-power applications. with this simple circuit it is not possible to tristate the bus and disconnect r1/r2. therefore one cannot switch off segments of the bus.
the max3372e-max3393e family of level translators solves these problems. figure 4 shows the simplified schematic of the max3373e, where two mosfets q4 and q5 have been added. q4 and q5 close for a short time during the rising edge and speed-up the low-to-high transition. minimum guaranteed data-rate for the max3373e is 8mbps, µp to 16mbps is possible if |vcc - vl| 30cm), it is necessary to use external pull-up resistors rpp. figure 8 shows the minimum value of rp, which is 1.7kω for rs = 0 and vdd = 5v. from this we find the minimum value for rpp to be 2.2kω, so that rpp in parallel with the internal pull-up of 10kω is 1.83kω.
figure 8. minimum value of rp as a function of supply voltage with the value of rsas a parameter, from i²c-specification.
in summary, the max3372e-max3393e are ideal solutions to solve the i²c or spi bus-level translation problems found in low-voltage systems. guaranteed data rates, low power requirements, low-supply-voltage operability, and small packages help solve the many problems facing designers in bus architectures today.
spi is a trademark of motorola, inc.
微型热保护器在管状电机的应用-「安的电子」
1%精度 1206封装 128种阻值 每种阻值50片 贴片电阻盒 R12E24-50
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Level Translators For SPI and
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a serial interface is often used for board-level communication between different integrated circuits, especially in space-constrained applications at low-to medium data-rates. the most popular serial interfaces are i²c and spi™.
this application note describes i²c and spi and some level-translation circuits that interface to them.
the spi-bus has 4 signals: active-low cs = active-low chip select, sclk = clock, din = data in, and dout = data out.
figure 1 illustrates the timing of these signals. the spi-specification has a clock polarity (cpol) and a clock phase (cpha) bit. figure 1 relates to the most common combination of these bits, cpol = 0 (data-transfer on the rising clock edge) and cpha = 0 (clock transitions in the middle of bit timing).
figure 1. signals and timing of the spi-interface.
several devices might be connected to the same bus, where all devices share the din and sclk-line. each device has a separate chip-select signal, so that the µp can address the appropriate part by the relevant active-low cs signal. if a chip does not talk back to the µp (e.g., dac), the dout-line is not needed. the spi-bus is well suited to data-rates to 20mbps. some devices (e.g., rtcs like the max6901) have a 3-wire interface, where the data-line is bi-directional. this interface is similar to spi.
the i²c-bus has 2 signals: scl = clock and sda = data in/out.
figure 2 illustrates the timing of the i²c-bus. each device has a unique 7-bit or 10-bit address. as the data-line is bi-directional, only 2 wires are required, which is an advantage in space-constrained applications or in designs where different parts of the circuit have to be optically isolated. data-rates for the i²c-bus are 100kbps, 400kbps, or even µp to 3.4mbps for the high-speed mode. the i²c-bus requires pull-up resistors rp, where the value of rp depends on the supply-voltage and the bus-capacitance (number of devices connected to the bus and length of the bus).
figure 2. signals and timing of the i²c-interface.
if a system has different supply voltages for the µp and for peripheral devices, suitable level translators are required to be able to use one of these serial interfaces. there are several reasons why today's systems have two or more supply-voltages. high-speed µps and dsps are implemented on the most advanced processes to get maximum performance with the lowest power consumption. these processes are often limited to supply voltages of 3v or less. typical core-voltages are 1.5v-2.5v. on the other hand, i/o-devices like da-and ad-converters might have a supply-voltage of 3.3v or 5v to achieve the required dynamic range. in portable and low-power applications there is another reason to have the µp run with the lowest possible supply voltage. current consumption of a typical microprocessor depends on clock frequency and supply voltage. one way to achieve low current consumption is therefore to reduce the supply voltage. this also leads to the situation where the µp runs from a different supply than other devices. another reason for different supply voltages might be the use of asics or fpgas together with a µp. for all these applications the designer needs a uni-or bi-directional level translator for the bus signals.
figure 3 shows a basic level translator with an n-channel mosfet. if neither q2 or q3 pulls the data-line low, vgs of q1 is 0v and data 1.8 has a level of 1.8v, data 3.3 is at 3.3v. if q2 pulls data 1.8 low, vgs of q1 is 1.8v and will turn on q1, pulling data 3.3 low. if q3 pulls data 3.3 low, the body diode of q1 will be forward-biased, pulling the source to 0.3v. vgs will be 1.5v and q1 will turn on, pulling data 1.8 low. so logic-levels are translated in both directions. we assume here that q2 has zero on-resistance. for a real application we would have to consider this on-resistance, which is 133ω worst-case for an i²c-compatible output (0.4v at 3ma) or 22ω for the 74lvc125 buffer (0.55v at 24ma). in this case the voltage vgs to turn on q1 would no longer be 1.8v, but would be lower, depending on r1 and the on-resistance of q1.
figure 3. basic level translator.
there are several problems associated with this circuit:
with vl being 1.8v or even lower, the choice of suitable mosfets with a low enough vgs threshold voltage is rather limited. one candidate might be the tn2501 from supertex. the slew-rate and, therefore, the maximum transmission rate depends on the value of r1/r2 and on the number of devices on the bus, which determines the capacitance. it is possible to increase the maximum transmission rate by choosing lower value resistors r1/r2. this will lead to higher current consumption, which is undesirable in portable/low-power applications. with this simple circuit it is not possible to tristate the bus and disconnect r1/r2. therefore one cannot switch off segments of the bus.
the max3372e-max3393e family of level translators solves these problems. figure 4 shows the simplified schematic of the max3373e, where two mosfets q4 and q5 have been added. q4 and q5 close for a short time during the rising edge and speed-up the low-to-high transition. minimum guaranteed data-rate for the max3373e is 8mbps, µp to 16mbps is possible if |vcc - vl| 30cm), it is necessary to use external pull-up resistors rpp. figure 8 shows the minimum value of rp, which is 1.7kω for rs = 0 and vdd = 5v. from this we find the minimum value for rpp to be 2.2kω, so that rpp in parallel with the internal pull-up of 10kω is 1.83kω.
figure 8. minimum value of rp as a function of supply voltage with the value of rsas a parameter, from i²c-specification.
in summary, the max3372e-max3393e are ideal solutions to solve the i²c or spi bus-level translation problems found in low-voltage systems. guaranteed data rates, low power requirements, low-supply-voltage operability, and small packages help solve the many problems facing designers in bus architectures today.
spi is a trademark of motorola, inc.
微型热保护器在管状电机的应用-「安的电子」
1%精度 1206封装 128种阻值 每种阻值50片 贴片电阻盒 R12E24-50
浅析红外系统和变频器在自动扶梯中的应用设计
从去年3月到今年6月，花费大多数国产手机的两倍时间还要多，OPPO Find X到底经历了什么才成功量产的？
浅谈电能质量电网谐波
Level Translators For SPI and
大负载为何成六轴机器人厂商必争之地？
如何在WINCC中使用报警声音？2种方式轻松实现！
提升储能系统性能的选择：BL302嵌入式ARM控制器
如何选购优质的端子线，有什么特点？
基于深度神经网络的比色传感器设计方案
四大“标签”背书，ADI积极扩建本地智能汽车生态圈
vivo Y19售价曝光，搭载联发科P65八核处理器
荣耀董事长万飚回应：仍在公司任职，未提及职位变更
解决CAN总线超强干扰的几个措施
辛巴辛有志华丽转身，推出的科技生活创造者平台HOLAX
Vicor高压DC-DC电源模块V300系列 可支持180~375V输入电压
充电桩剩余电流保护器的选用
热烈祝贺：四川美阔电子科技有限公司与ISweek工采网达成合作
理发店标志灯制作方法