DS3112 LRCLKx Low Speed Clock
abstract: the ds3112 ds3/e3 multiplex-framer has three multiplexed modes of operation. this application note describes how the device recovers the low-speed clock signals from the high-speed multiplexed signal for the three modes of operation. the note explains how the data present in the high-speed signal affects the recovery process.
introductionthis article describes how the ds3112 multiplex-framer recovers the low-speed clock signals from the high-speed multiplexed signal for the device's three multiplexed modes of operation. the first mode of operation is the recovery of the 28 ds1 clock signals from the ds3 signal in the m13 and c-bit parity modes. the second mode is the recovery of the 16 e1 clock signals from the e3 signal in the e13 mode. the third mode is the recovery of the 21 e1 clock signals from the ds3 signal in g.747 mode. when recovering the low-speed clocks, it is important to note that the actual data present in the high-speed signal affects the recovery process. for this reason when the term 'signal' is used by itself, it refers to the combined clock, data, and enable signals. any use of the terms 'clock', 'data', or 'enable' in conjunction with the signal refers to the individual signal component.
ds1 clock recovery for m13 and c-bit parity modesthe recovery of the 28 individual ds1 clocks from the ds3 signal is a complex three-stage process.
the first stage, the m23 stage, demultiplexes the ds3 signal into seven individual ds2 signals. instead of recovering the individual ds2 clocks, ds2 enables are created. each of the seven ds2 enables is in the active state for 84 x 7 + (84 or 83) ds3 clock periods per ds3 frame. the decision to recover the final 84 or 83 ds3 clock periods is based on the ds2 stuff bit control.
the second stage is the m12 stage which demultiplexes each of the seven ds2 signals into four ds1 signals for a total of 28 ds1 signals. as in the m23 stage, the m12 stage does not recover the individual ds1 clocks, but instead creates ds1 enables. each of the four ds1 enables is in the active state for 48 x 5 + (48 or 47) ds2 enable periods. the decision to recover the final 48 or 47 ds2 enable periods is based on the ds1 stuff bit control.
the third, and final, stage is the fifo stage which actually recreates the individual ds1 clocks. each of the ds1 clocks is created by dividing the ds3 clock (hrclk) by either 28 or 29. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the ds1 enable to write data into the fifo and the ds1 clock (lrclkx) to read data from the fifo. the correct ds1 clock rate is recovered by the fifo attempting to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 28' is chosen. if the amount of data is under the half-full mark, 'divide by 29' is chosen. a complete diagram of the clock-recovery mechanism is shown in figure 1.
figure 1. m13 and c-bit parity modes.
e1 clock recovery for e13 modethe recovery of the 16 individual e1 clocks from the e3 signal is also a complex three-stage process.
the first stage is the e23 stage which demultiplexes the e3 signal into four e2 signals. instead of recovering the individual e2 clocks, e2 enables are created. each of the four e2 enables is in the active state for 93 + 95 x 2 + (95 or 94) e3 clock periods per e3 frame. the decision to recover the final 95 or 94 e3 clock periods is based on the e2 stuff bit control.
the second stage is the e12 stage which demultiplexes each of the four e2 signals into four e1 signals for a total of 16 e1 signals. as in the e23 stage, the e12 stage does not recover the individual e1 clocks, but instead creates e1 enables. each of the four e1 enables is in the active state for 50 + 52 x 2 + (52 or 51) e2 enable periods. the decision to recover the final 52 or 51 e2 enable periods is based on the e1 stuff bit control.
the third, and final stage, is the fifo stage which actually recreates the individual e1 clocks. each of the e1 clocks is created by dividing the e3 clock (hrclk) by either 16 or 17. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the e1 enable to write data into the fifo and the e1 clock (lrclkx) to read data from the fifo. the correct e1 clock rate is recovered by the fifo which attempts to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 16' is chosen. if the amount of data is under the half-full mark, 'divide by 17' is chosen. a complete diagram on the clock-recovery mechanism is shown in figure 2.
figure 2. e13 mode.
e1 clock recovery for g.747 modethe recovery of the 21 individual e1 clocks from the ds3 signal is also a complex three-stage process.
the first stage is the m23 stage which demultiplexes the ds3 signal into seven ds2 signals. instead of recovering the individual ds2 clocks, ds2 enables are created. each of the seven ds2 enables is in the active state for 84 x 7 + (84 or 83) ds3 clock periods per ds3 frame. the decision to recover the final 84 or 83 ds3 clock periods is based on the ds2 stuff bit control.
the second stage is the g.747 stage which demultiplexes each of the seven ds2 signals into three e1 signals for a total of 21 e1 signals. as in the m23 stage, the g.747 stage does not recover the individual e1 clocks but instead creates e1 enables. each of the three e1 enables is in the active state for 53 + 55 x 3 + (55 or 54) ds2 enable periods. the decision to recover the final 55 or 54 ds2 enable periods is based on the e1 stuff bit control.
the third, and final, stage is the fifo stage which actually recreates the individual e1 clocks. each of the e1 clocks is created by dividing the ds3 clock (hrclk) by either 21 or 22. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the e1 enable to write data into the fifo and the e1 clock (lrclkx) to read data from the fifo. the correct e1 clock rate is recovered by the fifo which attempts to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 21' is chosen. if the amount of data is under the half-full mark, 'divide by 22' is chosen. a complete diagram on the clock-recovery mechanism is shown in figure 3.
figure 3. g.747 mode.
references
for further questions on the ds3112 low-speed clock recovery, please contact the telecommunication applications support team by email, telecom.support@dalsemi.com, or telephone at 01-972-371-6555.
for general information about the ds3112, please consult the data sheet.
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introductionthis article describes how the ds3112 multiplex-framer recovers the low-speed clock signals from the high-speed multiplexed signal for the device's three multiplexed modes of operation. the first mode of operation is the recovery of the 28 ds1 clock signals from the ds3 signal in the m13 and c-bit parity modes. the second mode is the recovery of the 16 e1 clock signals from the e3 signal in the e13 mode. the third mode is the recovery of the 21 e1 clock signals from the ds3 signal in g.747 mode. when recovering the low-speed clocks, it is important to note that the actual data present in the high-speed signal affects the recovery process. for this reason when the term 'signal' is used by itself, it refers to the combined clock, data, and enable signals. any use of the terms 'clock', 'data', or 'enable' in conjunction with the signal refers to the individual signal component.
ds1 clock recovery for m13 and c-bit parity modesthe recovery of the 28 individual ds1 clocks from the ds3 signal is a complex three-stage process.
the first stage, the m23 stage, demultiplexes the ds3 signal into seven individual ds2 signals. instead of recovering the individual ds2 clocks, ds2 enables are created. each of the seven ds2 enables is in the active state for 84 x 7 + (84 or 83) ds3 clock periods per ds3 frame. the decision to recover the final 84 or 83 ds3 clock periods is based on the ds2 stuff bit control.
the second stage is the m12 stage which demultiplexes each of the seven ds2 signals into four ds1 signals for a total of 28 ds1 signals. as in the m23 stage, the m12 stage does not recover the individual ds1 clocks, but instead creates ds1 enables. each of the four ds1 enables is in the active state for 48 x 5 + (48 or 47) ds2 enable periods. the decision to recover the final 48 or 47 ds2 enable periods is based on the ds1 stuff bit control.
the third, and final, stage is the fifo stage which actually recreates the individual ds1 clocks. each of the ds1 clocks is created by dividing the ds3 clock (hrclk) by either 28 or 29. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the ds1 enable to write data into the fifo and the ds1 clock (lrclkx) to read data from the fifo. the correct ds1 clock rate is recovered by the fifo attempting to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 28' is chosen. if the amount of data is under the half-full mark, 'divide by 29' is chosen. a complete diagram of the clock-recovery mechanism is shown in figure 1.
figure 1. m13 and c-bit parity modes.
e1 clock recovery for e13 modethe recovery of the 16 individual e1 clocks from the e3 signal is also a complex three-stage process.
the first stage is the e23 stage which demultiplexes the e3 signal into four e2 signals. instead of recovering the individual e2 clocks, e2 enables are created. each of the four e2 enables is in the active state for 93 + 95 x 2 + (95 or 94) e3 clock periods per e3 frame. the decision to recover the final 95 or 94 e3 clock periods is based on the e2 stuff bit control.
the second stage is the e12 stage which demultiplexes each of the four e2 signals into four e1 signals for a total of 16 e1 signals. as in the e23 stage, the e12 stage does not recover the individual e1 clocks, but instead creates e1 enables. each of the four e1 enables is in the active state for 50 + 52 x 2 + (52 or 51) e2 enable periods. the decision to recover the final 52 or 51 e2 enable periods is based on the e1 stuff bit control.
the third, and final stage, is the fifo stage which actually recreates the individual e1 clocks. each of the e1 clocks is created by dividing the e3 clock (hrclk) by either 16 or 17. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the e1 enable to write data into the fifo and the e1 clock (lrclkx) to read data from the fifo. the correct e1 clock rate is recovered by the fifo which attempts to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 16' is chosen. if the amount of data is under the half-full mark, 'divide by 17' is chosen. a complete diagram on the clock-recovery mechanism is shown in figure 2.
figure 2. e13 mode.
e1 clock recovery for g.747 modethe recovery of the 21 individual e1 clocks from the ds3 signal is also a complex three-stage process.
the first stage is the m23 stage which demultiplexes the ds3 signal into seven ds2 signals. instead of recovering the individual ds2 clocks, ds2 enables are created. each of the seven ds2 enables is in the active state for 84 x 7 + (84 or 83) ds3 clock periods per ds3 frame. the decision to recover the final 84 or 83 ds3 clock periods is based on the ds2 stuff bit control.
the second stage is the g.747 stage which demultiplexes each of the seven ds2 signals into three e1 signals for a total of 21 e1 signals. as in the m23 stage, the g.747 stage does not recover the individual e1 clocks but instead creates e1 enables. each of the three e1 enables is in the active state for 53 + 55 x 3 + (55 or 54) ds2 enable periods. the decision to recover the final 55 or 54 ds2 enable periods is based on the e1 stuff bit control.
the third, and final, stage is the fifo stage which actually recreates the individual e1 clocks. each of the e1 clocks is created by dividing the ds3 clock (hrclk) by either 21 or 22. the selection of the divisor is based on the amount of data currently stored in the fifo. the fifo uses the e1 enable to write data into the fifo and the e1 clock (lrclkx) to read data from the fifo. the correct e1 clock rate is recovered by the fifo which attempts to keep the amount of data in the fifo centered at the half-full mark. if the amount of data is over the half-full mark, 'divide by 21' is chosen. if the amount of data is under the half-full mark, 'divide by 22' is chosen. a complete diagram on the clock-recovery mechanism is shown in figure 3.
figure 3. g.747 mode.
references
for further questions on the ds3112 low-speed clock recovery, please contact the telecommunication applications support team by email, telecom.support@dalsemi.com, or telephone at 01-972-371-6555.
for general information about the ds3112, please consult the data sheet.
北京已初步形成完整的工业互联网产业体系
Lego携手Autodesk推3D互动设计软件，加强可编程机器人用户体验
配置文件和例程文件的使用
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