SpinalHDL语法之Bool类型
作为spinalhdl语法篇的第一节，我们也从最简单的开始。
bool类型定义bool类型就是verilog中的单bit类型，定义方式如下：
syntaxdescriptionreturn
bool() 创建bool类型变量 bool
true 创建bool类型变量，并赋值true bool
false 创建bool类型变量，并赋值false bool
bool(value: boolean) 创建bool类型变量，并使用scala表达式赋值 bool
example：
val a = bool()val b = trueval c = falseval d = bool( 1 > 2)生成的verilog代码如下：
wire a;wire b;wire c;wire d;assign b = 1'b1;assign c = 1'b0;assign d = 1'b0;逻辑运算下图为官方的逻辑运算解释，也不翻译了，很容易理解。
operatordescriptionreturn type
!x logical not bool
x && y logical and bool
x & y logical and bool
x y
x y logical or
x ^ y logical xor bool
x.set[()] set x to true bool
x.clear[()] set x to false bool
x.setwhen(cond) set x when cond is true bool
x.clearwhen(cond) clear x when cond is true bool
x.risewhen(cond) set x when x is false and cond is true bool
x.fallwhen(cond) clear x when x is true and cond is true bool
val e = a & b val f = a | b val g = a ^ b val h = !a val i = bool() i.set() val j = bool() j.clear() val k = true #这里必须有初值，否则下一句会报错 k.clearwhen(b) val l = true when(b){ l := false } val m = reginit(false) #关于寄存器类型，这里先熟悉一下，后面章节会讲到 m.risewhen(b)边缘检测operatordescriptionreturn type
x.edge[()] return true when x changes state bool
x.edge(initat: bool) same as x.edge but with a reset value bool
x.rise[()] return true when x was low at the last cycle and is now high bool
x.rise(initat: bool) same as x.rise but with a reset value bool
x.fall[()] return true when x was high at the last cycle and is now low bool
x.fall(initat: bool) same as x.fall but with a reset value bool
x.edges[()] return a bundle (rise, fall, toggle) booledges
x.edges(initat: bool) same as x.edges but with a reset value booledges
val a = bool()val b = falsewhen(a.edge()){b := true}val c = a.edge(false)转换后的代码为：
module demobool ( input clk, input reset); wire a; reg b; reg a_regnext; wire when_demobool_l35; reg a_regnext_1; wire c; always @(*) begin b = 1'b0; if(when_demobool_l35) begin b = 1'b1; end end assign when_demobool_l35 = (a ^ a_regnext); assign c = (a ^ a_regnext_1); always @(posedge clk) begin a_regnext <= a; end always @(posedge clk or posedge reset) begin if(reset) begin a_regnext_1 <= 1'b0; end else begin a_regnext_1 <= a; end endendmoduleval edgebundle = mybool_2.edges(false)when(edgebundle.rise) { // do something when a rising edge is detected}when(edgebundle.fall) { // do something when a falling edge is detected}when(edgebundle.toggle) { // do something at each edge}数值比对operatordescriptionreturn type
x === y equality bool
x =/= y inequality bool
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bool类型定义bool类型就是verilog中的单bit类型，定义方式如下：
syntaxdescriptionreturn
bool() 创建bool类型变量 bool
true 创建bool类型变量，并赋值true bool
false 创建bool类型变量，并赋值false bool
bool(value: boolean) 创建bool类型变量，并使用scala表达式赋值 bool
example：
val a = bool()val b = trueval c = falseval d = bool( 1 > 2)生成的verilog代码如下：
wire a;wire b;wire c;wire d;assign b = 1'b1;assign c = 1'b0;assign d = 1'b0;逻辑运算下图为官方的逻辑运算解释，也不翻译了，很容易理解。
operatordescriptionreturn type
!x logical not bool
x && y logical and bool
x & y logical and bool
x y
x y logical or
x ^ y logical xor bool
x.set[()] set x to true bool
x.clear[()] set x to false bool
x.setwhen(cond) set x when cond is true bool
x.clearwhen(cond) clear x when cond is true bool
x.risewhen(cond) set x when x is false and cond is true bool
x.fallwhen(cond) clear x when x is true and cond is true bool
val e = a & b val f = a | b val g = a ^ b val h = !a val i = bool() i.set() val j = bool() j.clear() val k = true #这里必须有初值，否则下一句会报错 k.clearwhen(b) val l = true when(b){ l := false } val m = reginit(false) #关于寄存器类型，这里先熟悉一下，后面章节会讲到 m.risewhen(b)边缘检测operatordescriptionreturn type
x.edge[()] return true when x changes state bool
x.edge(initat: bool) same as x.edge but with a reset value bool
x.rise[()] return true when x was low at the last cycle and is now high bool
x.rise(initat: bool) same as x.rise but with a reset value bool
x.fall[()] return true when x was high at the last cycle and is now low bool
x.fall(initat: bool) same as x.fall but with a reset value bool
x.edges[()] return a bundle (rise, fall, toggle) booledges
x.edges(initat: bool) same as x.edges but with a reset value booledges
val a = bool()val b = falsewhen(a.edge()){b := true}val c = a.edge(false)转换后的代码为：
module demobool ( input clk, input reset); wire a; reg b; reg a_regnext; wire when_demobool_l35; reg a_regnext_1; wire c; always @(*) begin b = 1'b0; if(when_demobool_l35) begin b = 1'b1; end end assign when_demobool_l35 = (a ^ a_regnext); assign c = (a ^ a_regnext_1); always @(posedge clk) begin a_regnext <= a; end always @(posedge clk or posedge reset) begin if(reset) begin a_regnext_1 <= 1'b0; end else begin a_regnext_1 <= a; end endendmoduleval edgebundle = mybool_2.edges(false)when(edgebundle.rise) { // do something when a rising edge is detected}when(edgebundle.fall) { // do something when a falling edge is detected}when(edgebundle.toggle) { // do something at each edge}数值比对operatordescriptionreturn type
x === y equality bool
x =/= y inequality bool
华为荣耀9什么时候上市?荣耀9:小米6的真正对手发布正式确定,双摄+麒麟960,价格2499元,吃瓜群众又不安静了
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