Inexpensive Peak Detector Feat
abstract: this circuit, which uses a digital potentiometer (pot) and a comparator, features droopless operation that is not normally associated with peak detectors that have traditionally used rectifiers and sample-and-holds (s/h).
most peak detectors employ a rectifier and a sample-and-hold circuit, which is prone to output droop. in an alternative approach, shown in the figure below, a 5-bit digital potentiometer with a servo loop is used to create an inexpensive peak detector with a logic-level reset input and no output droop.
comparator control of ic1's chip-select input ensures that the digital potentiometer becomes active only when vin exceeds the vout level currently latched, and r1 ensures that the potentiometer increments upward (rather than downward) as a result. when vi rises above vout, the comparator output (ic2) swings low and selects ic1, allowing the wiper position to increment upwards with each high-to-low transition of the clock (inc*). when vout reaches vin, the comparator output goes high and latches vout at that level.
vout ranges between the voltage levels connected to the upper and lower extremes of the digital pot (5v and 0v in this case) in 32 equally spaced increments. by reducing this vout range, the size of an lsb can be decreased, thereby increasing the output resolution.
most peak detectors employ a capacitor for holding the output voltage, and the droop (slow change) in vout caused by the capacitor's leakage current is particularly noticeable with low frequency or low duty cycle signals. the primary advantage of this circuit is the complete absence of such output droop. it holds the output level indefinitely, making it useful as a long-term memory.
unlike peak detectors that use a capacitor to hold the output voltage, this design includes a digital potentiometer (ic1) that holds the output level indefinitely, without droop.
*this indicates the inverse of the signal.
a similar version of this article appeared in the may 15, 2000 issue of electronic design.
澳柯玛坚守为提升生活品质 开发出冰玲珑BD-156WG风冷立式冷柜
2017年必备数码产品 笔记本手机相机集合！
全打印制备多层嵌入式柔性电路方面的技术发展
全球首个面向5G Edge-Cloud的解决方案已实现商用部署
微芯科技拟8.29亿收购标准微系统公司(SMSC)
Inexpensive Peak Detector Feat
国内争先上马智能城市项目多达500+,到底什么技术模式适合城市
信号差怎么办，手机信号放大器可轻松帮您解决问题
智能门锁的晶振如何选择合适的频率？
加拿大交易运营商TMX集团正在推出一种加密货币回扣业务
核心网通过引入SCEF可以满足5G多样化业务的需求
都逃不过“真香定律”！搭载144Hz竞速屏的iQOO Neo3你猜多少钱
广东联通携手华为已完成了智能城域网综合业务承载的功能验证
如何利用NX4024K实现汽车警报监控系统的设计
社交应用程序ParlerCEO：禁令后所有供应商都放弃其公司
谈谈中国激光的技术升级之路
从入门到高手，电子工程师必备的15款工具！
《2019物联网行业100强》榜单新鲜出炉，SIMBOSS荣登100强
室外光缆冷接技术存在明显缺陷
STM32U5系列TIMER+DMA+DAC应用演示
most peak detectors employ a rectifier and a sample-and-hold circuit, which is prone to output droop. in an alternative approach, shown in the figure below, a 5-bit digital potentiometer with a servo loop is used to create an inexpensive peak detector with a logic-level reset input and no output droop.
comparator control of ic1's chip-select input ensures that the digital potentiometer becomes active only when vin exceeds the vout level currently latched, and r1 ensures that the potentiometer increments upward (rather than downward) as a result. when vi rises above vout, the comparator output (ic2) swings low and selects ic1, allowing the wiper position to increment upwards with each high-to-low transition of the clock (inc*). when vout reaches vin, the comparator output goes high and latches vout at that level.
vout ranges between the voltage levels connected to the upper and lower extremes of the digital pot (5v and 0v in this case) in 32 equally spaced increments. by reducing this vout range, the size of an lsb can be decreased, thereby increasing the output resolution.
most peak detectors employ a capacitor for holding the output voltage, and the droop (slow change) in vout caused by the capacitor's leakage current is particularly noticeable with low frequency or low duty cycle signals. the primary advantage of this circuit is the complete absence of such output droop. it holds the output level indefinitely, making it useful as a long-term memory.
unlike peak detectors that use a capacitor to hold the output voltage, this design includes a digital potentiometer (ic1) that holds the output level indefinitely, without droop.
*this indicates the inverse of the signal.
a similar version of this article appeared in the may 15, 2000 issue of electronic design.
澳柯玛坚守为提升生活品质 开发出冰玲珑BD-156WG风冷立式冷柜
2017年必备数码产品 笔记本手机相机集合！
全打印制备多层嵌入式柔性电路方面的技术发展
全球首个面向5G Edge-Cloud的解决方案已实现商用部署
微芯科技拟8.29亿收购标准微系统公司(SMSC)
Inexpensive Peak Detector Feat
国内争先上马智能城市项目多达500+,到底什么技术模式适合城市
信号差怎么办，手机信号放大器可轻松帮您解决问题
智能门锁的晶振如何选择合适的频率？
加拿大交易运营商TMX集团正在推出一种加密货币回扣业务
核心网通过引入SCEF可以满足5G多样化业务的需求
都逃不过“真香定律”！搭载144Hz竞速屏的iQOO Neo3你猜多少钱
广东联通携手华为已完成了智能城域网综合业务承载的功能验证
如何利用NX4024K实现汽车警报监控系统的设计
社交应用程序ParlerCEO：禁令后所有供应商都放弃其公司
谈谈中国激光的技术升级之路
从入门到高手，电子工程师必备的15款工具！
《2019物联网行业100强》榜单新鲜出炉，SIMBOSS荣登100强
室外光缆冷接技术存在明显缺陷
STM32U5系列TIMER+DMA+DAC应用演示