DS31256的初始化步骤
摘要：ds31256 envoy hdlc控制器在发送数据包之前的初始化顺序。
概述按照设计，ds31256上电以后不会控制pci总线。所有的物理端口(端口0至15)发送全1 (非hdlc空闲码)，因此在上电之后ds31256处于空闲状态。另一方面，ds31256可以初始化基于ram的存储器，包括直接和间接的，用于存储内部状态机的状态。ds31256有许多非常复杂的状态机和相互作用的功能模块，因此上电之后，在发送和接收任何数据包之前，所有的这些内部寄存器/ram必须初始化到一个已知状态。建议使用者在发送数据包之前按照表1的步骤进行初始化。
表1. ds31256的初始化步骤 initialization step comments
1. system reset.
system reset can be invoked by either hardware action via the prst-bar signal or software action via the rst control bit in the master reset and id register; all the internal device configuration registers are set to zero (0000h).
2. configure local bus bridge mode control register (lbbmc), if ds31256 is used in bridge mode.
please note that these registers are not affected by a software-invoked system reset. it will be forced to all zeros only by hardware reset.
3. initialize the pci configuration registers.
achieved by asserting the pidsel signal.
4. master software reset.
master software reset in mrid register.
5. initialize all indirect registers to zero.
it is recommended that all the indirect registers be set to 0000h. see table 2 for a list of all indirect registers.
6. master software reset.
master software reset in mrid register.
7. configure the device for operation.
program all the necessary registers, which includes the layer one, hdlc, fifo, and dma registers, but except:
1. ports are disabled; keep layer-one ports off by leaving the tfda1 bits to 0 (default state) in tp[n]cr register.
2. hdlc channels are disabled.
3. dma and dma channels are disabled.
4. in high-speed unchannelized mode, set it to low-speed unchannelized mode in the rp[n]cr register and enable it to high-speed unchannelized mode in step 12 (see below).
8. enable the hdlc channels.
done via the rchen and tchen bits in the r[n]cfg[j] and t[n]cfg[j] registers.
9. load the dma descriptors.
indicate to the dma where packet data can be written and where pending data (if any) resides.
10. enable the dmas.
done via the rde and tde control bits in the master configuration (mc) register.
11. enable dma for each hdlc channel.
done via the channel-enable bit in the receive and transmit configuration ram.
12. turns on hdlc channels.
enable and allow ports to transmit normally, set tfda1 bits to 1 in tp[n]cr registers. note: for high-speed unchannelized mode only, enable high-speed unchannelized in rp[n]cr register.
13. wait enough time for all configurations to take effect.
it is going to take a minimum of 500µs or 768 rc and tc clock cycles (which ever is longer) before packet data can be processed.
注意：建议ds31256上电之后进行 “硬件复位”。
表2. 间接寄存器 offset/address register name number of indirect registers data sheet section
0x3xx channelized port data indirect select (cp0rdis to cp15rdis) 6144 (16 ports x 128 ds0 channels x 3 registers for each ds0 channel) 6.3
0x400 receive hdlc channel definition indirect select (rhcdis) 256 (one for each hdlc channel) 7.2
0x480 transmit hdlc channel definition indirect select (thcdis) 256 (one for each hdlc channel) 7.2
0x770 receive dma configuration indirect select (rdmacis) 1536 (one for each hdlc channel) 9.3.5
0x870 transmit dma configuration indirect select (tdmacis) 3072 (one for each hdlc channel) 9.3.5
0x900 receive fifo staring block pointer indirect select (rfsbpis) 256 (one for each hdlc channel) 8.2
0x910 receive fifo block pointer indirect select (rfbpis) 1024 (one for each fifo block) 8.2
0x920 receive fifo high watermark indirect select (rfhwmis) 256 (one for each hdlc channel) 8.2
0x980 transmit fifo staring block pointer (tfsbpis) 256 (one for each hdlc channel) 8.2
0x990 transmit fifo block pointer indirect select (tfbpis) 1024 (one for each fifo block) 8.2
0x9a0 transmit fifo low watermark indirect select (tflwmis) 256 (one for each hdlc channel) 8.2
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概述按照设计，ds31256上电以后不会控制pci总线。所有的物理端口(端口0至15)发送全1 (非hdlc空闲码)，因此在上电之后ds31256处于空闲状态。另一方面，ds31256可以初始化基于ram的存储器，包括直接和间接的，用于存储内部状态机的状态。ds31256有许多非常复杂的状态机和相互作用的功能模块，因此上电之后，在发送和接收任何数据包之前，所有的这些内部寄存器/ram必须初始化到一个已知状态。建议使用者在发送数据包之前按照表1的步骤进行初始化。
表1. ds31256的初始化步骤 initialization step comments
1. system reset.
system reset can be invoked by either hardware action via the prst-bar signal or software action via the rst control bit in the master reset and id register; all the internal device configuration registers are set to zero (0000h).
2. configure local bus bridge mode control register (lbbmc), if ds31256 is used in bridge mode.
please note that these registers are not affected by a software-invoked system reset. it will be forced to all zeros only by hardware reset.
3. initialize the pci configuration registers.
achieved by asserting the pidsel signal.
4. master software reset.
master software reset in mrid register.
5. initialize all indirect registers to zero.
it is recommended that all the indirect registers be set to 0000h. see table 2 for a list of all indirect registers.
6. master software reset.
master software reset in mrid register.
7. configure the device for operation.
program all the necessary registers, which includes the layer one, hdlc, fifo, and dma registers, but except:
1. ports are disabled; keep layer-one ports off by leaving the tfda1 bits to 0 (default state) in tp[n]cr register.
2. hdlc channels are disabled.
3. dma and dma channels are disabled.
4. in high-speed unchannelized mode, set it to low-speed unchannelized mode in the rp[n]cr register and enable it to high-speed unchannelized mode in step 12 (see below).
8. enable the hdlc channels.
done via the rchen and tchen bits in the r[n]cfg[j] and t[n]cfg[j] registers.
9. load the dma descriptors.
indicate to the dma where packet data can be written and where pending data (if any) resides.
10. enable the dmas.
done via the rde and tde control bits in the master configuration (mc) register.
11. enable dma for each hdlc channel.
done via the channel-enable bit in the receive and transmit configuration ram.
12. turns on hdlc channels.
enable and allow ports to transmit normally, set tfda1 bits to 1 in tp[n]cr registers. note: for high-speed unchannelized mode only, enable high-speed unchannelized in rp[n]cr register.
13. wait enough time for all configurations to take effect.
it is going to take a minimum of 500µs or 768 rc and tc clock cycles (which ever is longer) before packet data can be processed.
注意：建议ds31256上电之后进行 “硬件复位”。
表2. 间接寄存器 offset/address register name number of indirect registers data sheet section
0x3xx channelized port data indirect select (cp0rdis to cp15rdis) 6144 (16 ports x 128 ds0 channels x 3 registers for each ds0 channel) 6.3
0x400 receive hdlc channel definition indirect select (rhcdis) 256 (one for each hdlc channel) 7.2
0x480 transmit hdlc channel definition indirect select (thcdis) 256 (one for each hdlc channel) 7.2
0x770 receive dma configuration indirect select (rdmacis) 1536 (one for each hdlc channel) 9.3.5
0x870 transmit dma configuration indirect select (tdmacis) 3072 (one for each hdlc channel) 9.3.5
0x900 receive fifo staring block pointer indirect select (rfsbpis) 256 (one for each hdlc channel) 8.2
0x910 receive fifo block pointer indirect select (rfbpis) 1024 (one for each fifo block) 8.2
0x920 receive fifo high watermark indirect select (rfhwmis) 256 (one for each hdlc channel) 8.2
0x980 transmit fifo staring block pointer (tfsbpis) 256 (one for each hdlc channel) 8.2
0x990 transmit fifo block pointer indirect select (tfbpis) 1024 (one for each fifo block) 8.2
0x9a0 transmit fifo low watermark indirect select (tflwmis) 256 (one for each hdlc channel) 8.2
与ADC接口：电源，第3部分
数据模型有哪些种类
安达发|揭秘五金制造业的APS高级计划和排程系统
布局5G通信、汽车电子 苹果A股供应链的自救
三极插头的定义几作用
DS31256的初始化步骤
5G竞争趋于白热化，中企开始积极进行产业布局
中国移动董事长杨杰对5G全球的发展提出了四点建议
xenomai+linux双内核下的时钟管理机制
OpenAI和微软下场造AI芯片 首款自研AI芯片11月上线！
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奶茶背后的直线电机炒茶机
开关电源如何进行设计的部分细节
通过多种接口总线与计算机实现自动检定/校准测试系统的设计
人工智能版“薄雾君” 人工智能植物种类识别
带有A9-9820 APU的无名主板已经出现在全球速卖通上
挪亚检测认证与TÜV南德达成战略合作，携手深耕TIC行业
魅族千元机是最好的手机：魅蓝5S、魅蓝Note5，你更看好谁？
特朗普做梦都想创造就业机会 可还得过机器人这关
PLC的扫描工作过程