DS21352/DS21552与DS2152单芯片收发器-D
abstract: this application note will help with the migration from a current design using the ds2152 single chip transceiver (sct) to one using the ds21352 or ds21552 sct. these two devices are foot print compatible which allows the ds2152 to be replaced with only minor modifications to both the hardware and software. some of the benefits of the migration to the ds21352 or ds21552 are that these devices have a more advanced hdlc, support jtag test functions, multiple devices can communicate on a single high-speed bus, and operate at 3.3 volts with 5.0 volt tolerant i/o. to take advantage of these new functions, the application note outlines the specific hardware and software differences. it also indicates the specific sections of the ds21352 and ds21552 data sheet which have more information on the new functions what are available.
1. introductionthis application note highlights the differences between the ds21352/ds21552 and the ds2152. the ds21352/ds21552 is a superset of the ds2152 maintaining a consistent pin out and register set. all of the original features of the ds2152 have been retained and software created for the ds2152 is transferable to the ds21352/ds21552 with minimal effort. the ds21352 and ds21552 are functionally equivalent with the only difference being the required supply voltage ?ethe ds21352 operates at 3.3v and the ds21552 operates at 5v.
2. additional functionality new features data sheet section
hdlc controller
buffer depth increased from 16 to 64 bytes
hdlc over ds0 functionality added 15
jtag 19
8 mbps interleaved pcm bus operation 20
3.3v operation with 5v tolerant i/o (for ds21352) 23
3. changes in register definitionswhen implementing the new features of the ds21352/ds21552, a priority was placed on preserving the ds2152’s register map to facilitate code migration from existing ds2152 designs. this section highlights register additions and differences found in the ds21352/ds21552.
3.1 new feature register usagehighlights specific registers related to new features. each item can be found in the data sheet under the listed sections.
3.1.1 hdlc ds0 control (section 15)
register address description
rdc1 90h receive hdlc ds0 control register 1
rdc2 91h receive hdlc ds0 control register 2
tdc1 92h transmit hdlc ds0 control register 1
tdc2 93h transmit hdlc ds0 control register 2
3.1.2 interleaved pcm bus operation (section 20)
register address description
ibo 94h interleave bus operation
3.2 bit assignment changes within existing registershighlights bit locations in the ds21352/ds21552 which have changed from the ds2152.
register bit # ds2152 symbol ds2152 description ds21352/ds21552 symbol ds21352/ds21552 description
ccr3 7 esmdm elastic store
minimum delay
mode resmdm rx elastic store
minimum delay mode
ccr3 6 esr elastic store reset tclksrc tx clock source select
ccr3 0 n/a not assigned tesmdm tx elastic store
minimum delay mode
ccr6 6 n/a not assigned resalgn rx elastic store align
ccr6 5 n/a not assigned tesalgn tx elastic store align
ccr7 5 n/a not assigned resr rx elastic store reset
ccr7 4 n/a not assigned tesr tx elastic store reset
4. changes in device pin out 4.1 package typesthe ds2152 and ds21352/ds21552 are both offered in a 100 pin 14 x 14 x 1.4mm lqfp. values listed are for body dimensions.
4.2 device pin differences4.2.1 jtag pins
pin # ds21352/ds21552 ds2152 description
2 jtms nc ieee 1149.1 test mode select
4 jtclk nc ieee 1149.1 test clock signal
5 jtrst nc ieee 1149.1 test reset
7 jtdi nc ieee 1149.1 test data input
10 jtdo nc ieee 1149.1 test data output
4.2.2 interleaved pcm bus pins
pin # ds21352/ds21552 ds2152 description
36 ci nc carry in
54 co nc carry out
4.2.3 framer mode select pin
pin # ds21352/ds21552 ds2152 description
76 fms nc framer mode select
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持久存储将会带来什么好处
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浅析MIMO的帧结构思路
邬贺铨：对于移动基站的辐射担心是多余的
有方科技在物联网领域的应用和优势探讨
1. introductionthis application note highlights the differences between the ds21352/ds21552 and the ds2152. the ds21352/ds21552 is a superset of the ds2152 maintaining a consistent pin out and register set. all of the original features of the ds2152 have been retained and software created for the ds2152 is transferable to the ds21352/ds21552 with minimal effort. the ds21352 and ds21552 are functionally equivalent with the only difference being the required supply voltage ?ethe ds21352 operates at 3.3v and the ds21552 operates at 5v.
2. additional functionality new features data sheet section
hdlc controller
buffer depth increased from 16 to 64 bytes
hdlc over ds0 functionality added 15
jtag 19
8 mbps interleaved pcm bus operation 20
3.3v operation with 5v tolerant i/o (for ds21352) 23
3. changes in register definitionswhen implementing the new features of the ds21352/ds21552, a priority was placed on preserving the ds2152’s register map to facilitate code migration from existing ds2152 designs. this section highlights register additions and differences found in the ds21352/ds21552.
3.1 new feature register usagehighlights specific registers related to new features. each item can be found in the data sheet under the listed sections.
3.1.1 hdlc ds0 control (section 15)
register address description
rdc1 90h receive hdlc ds0 control register 1
rdc2 91h receive hdlc ds0 control register 2
tdc1 92h transmit hdlc ds0 control register 1
tdc2 93h transmit hdlc ds0 control register 2
3.1.2 interleaved pcm bus operation (section 20)
register address description
ibo 94h interleave bus operation
3.2 bit assignment changes within existing registershighlights bit locations in the ds21352/ds21552 which have changed from the ds2152.
register bit # ds2152 symbol ds2152 description ds21352/ds21552 symbol ds21352/ds21552 description
ccr3 7 esmdm elastic store
minimum delay
mode resmdm rx elastic store
minimum delay mode
ccr3 6 esr elastic store reset tclksrc tx clock source select
ccr3 0 n/a not assigned tesmdm tx elastic store
minimum delay mode
ccr6 6 n/a not assigned resalgn rx elastic store align
ccr6 5 n/a not assigned tesalgn tx elastic store align
ccr7 5 n/a not assigned resr rx elastic store reset
ccr7 4 n/a not assigned tesr tx elastic store reset
4. changes in device pin out 4.1 package typesthe ds2152 and ds21352/ds21552 are both offered in a 100 pin 14 x 14 x 1.4mm lqfp. values listed are for body dimensions.
4.2 device pin differences4.2.1 jtag pins
pin # ds21352/ds21552 ds2152 description
2 jtms nc ieee 1149.1 test mode select
4 jtclk nc ieee 1149.1 test clock signal
5 jtrst nc ieee 1149.1 test reset
7 jtdi nc ieee 1149.1 test data input
10 jtdo nc ieee 1149.1 test data output
4.2.2 interleaved pcm bus pins
pin # ds21352/ds21552 ds2152 description
36 ci nc carry in
54 co nc carry out
4.2.3 framer mode select pin
pin # ds21352/ds21552 ds2152 description
76 fms nc framer mode select
电瓶修复技术加盟真假
大联大将举办首届智能飞行器设计大赛
海尔HP-2998B,HP-2928技改项目（必改项目）
大唐移动将联合中国移动正式启动国内高校首个5G智能网联示范基地
新贵GX1-R鼠标评测 性能良好做工严谨设计十分周到
DS21352/DS21552与DS2152单芯片收发器-D
中国移动5G赋能VR产业，解决了VR发展的两大痛点
夏季触电事故多发 佳岚智能让用电更安全
沪硅产业:将建立300mm SOI硅片的生产能力
如何查看各个模块的资源占用情况呢
低噪声、超低温度漂移系数的电压基准芯片LTR3312
华为在5G RAN的产品能力整体表现中四个维度的评估中都是第一
物联网网络安全威胁怎样防范
手机市场踏入冰封期 生物识别和AI或将成2018破冰利器
持久存储将会带来什么好处
IEEE消费电子协会-移动设备增强现实标准工作组宣布正式成立
台湾DRAM启示录：11年白忙一场
浅析MIMO的帧结构思路
邬贺铨：对于移动基站的辐射担心是多余的
有方科技在物联网领域的应用和优势探讨