建立快速电压瞬态-Creating Fast Line Tr
an integrated circuit's response to fast transients on its input supply is often an important measurement to take. if the device under test (dut) is a micro-power device and doesn't require an input bypass capacitor, simply drive the power-supply input with a 50ω terminated function generator. however, as the current requirements and capacitance are increased, this no longer provides acceptable results.
one solution to obtaining this fast transient into large capacitive loads is to make an open-loop buffer. because an open-loop buffer has no feedback, it is insensitive to capacitive loads and can be designed to meet most current requirements. important criteria for this buffer include high slew rate, high output drive, low offset voltage, low distortion, and thermal compensation.
the circuit in the figure below satisfies these requirements. it is similar to the classic bjt buffer with a few modifications. because the transistors used are not on a single monolithic die, some means has to be provided to adjust the bias. furthermore, the circuit must have some method to keep this bias constant over temperature.
figure 1. open-loop buffer schematic.
the circuit consists of three major blocks. there is a high-impedance complementary input stage, followed by a vbe multiplier for bias adjustment, and then a complementary darlington output stage. the input stage and the vbe multiplier are biased with constant current sources, whereas the output stage is biased by the output of the vbe multiplier.
the key to connecting the input stage to the vbe multiplier and the output stage is the inclusion of some series resistance via resistors r7 and r8. this allows the vbe multiplier to control the output stage bias without fighting the bias levels of the input stage. this becomes a factor as the output stage heats up due to load requirements. if the series resistors were not included, the input stage would overbias the output stage at elevated temperatures. because the vbe multiplier is mounted on the output heatsink, it thermally tracks the output stage, eliminating thermal runaway.
this circuit is designed for bipolar power supplies above the maximum output by about 5v and below the minimum output by about 5v. operation at +15v and -5v provides good performance. note that multiple grounds have been included on the board. the input supplies should use a short pair of heavy-gauge wire to the pcb. do not share these grounds with any other circuitry. the output should be connected to the dut input with very short heavy-gauge wires. these wires will carry transient currents in excess of 10a and should be sized accordingly.
the buffer was designed with a high input impedance to have flexible drive requirements. don't connect the output of the buffer to the input of the dut without a driving signal on the buffer input. if the output voltages are under ±5v, use a 50ω terminator right at the buffer input. if the output is up to 10v, run the pulse generator unterminated to get this voltage. voltages beyond this will require the addition of an external amplifier. the maximum supply voltages for the buffer are |v+ - v-| < 40v.
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one solution to obtaining this fast transient into large capacitive loads is to make an open-loop buffer. because an open-loop buffer has no feedback, it is insensitive to capacitive loads and can be designed to meet most current requirements. important criteria for this buffer include high slew rate, high output drive, low offset voltage, low distortion, and thermal compensation.
the circuit in the figure below satisfies these requirements. it is similar to the classic bjt buffer with a few modifications. because the transistors used are not on a single monolithic die, some means has to be provided to adjust the bias. furthermore, the circuit must have some method to keep this bias constant over temperature.
figure 1. open-loop buffer schematic.
the circuit consists of three major blocks. there is a high-impedance complementary input stage, followed by a vbe multiplier for bias adjustment, and then a complementary darlington output stage. the input stage and the vbe multiplier are biased with constant current sources, whereas the output stage is biased by the output of the vbe multiplier.
the key to connecting the input stage to the vbe multiplier and the output stage is the inclusion of some series resistance via resistors r7 and r8. this allows the vbe multiplier to control the output stage bias without fighting the bias levels of the input stage. this becomes a factor as the output stage heats up due to load requirements. if the series resistors were not included, the input stage would overbias the output stage at elevated temperatures. because the vbe multiplier is mounted on the output heatsink, it thermally tracks the output stage, eliminating thermal runaway.
this circuit is designed for bipolar power supplies above the maximum output by about 5v and below the minimum output by about 5v. operation at +15v and -5v provides good performance. note that multiple grounds have been included on the board. the input supplies should use a short pair of heavy-gauge wire to the pcb. do not share these grounds with any other circuitry. the output should be connected to the dut input with very short heavy-gauge wires. these wires will carry transient currents in excess of 10a and should be sized accordingly.
the buffer was designed with a high input impedance to have flexible drive requirements. don't connect the output of the buffer to the input of the dut without a driving signal on the buffer input. if the output voltages are under ±5v, use a 50ω terminator right at the buffer input. if the output is up to 10v, run the pulse generator unterminated to get this voltage. voltages beyond this will require the addition of an external amplifier. the maximum supply voltages for the buffer are |v+ - v-| < 40v.
研究人员共同提出了一种面向目标检测任务的新模块Res2Net
史陶比尔全新推出紧凑多芯型充电连接器AGV-CC6
低介电耐高温200C绝缘透波氮化硼涂（填）料
兽药残留快速检测仪的原理是什么
6G通信关键技术之太赫兹技术
建立快速电压瞬态-Creating Fast Line Tr
Redmi Note8:2019年全球最畅销机型第二
终于轮到丰田出手 投入数十亿美元开发人工智能无人驾驶
在Zynq SoC上实现双核非对称的多进程处理模式
移动办公用什么？Core i7 vPro，开启高性能移动办公
选通报警器
SLOT 1插槽
云计算国内外发展现状及应用前景分析
DIGITAL DAY 2022解决方案看点 虚拟数字人
无线耳机和有线耳机哪个好，公认最好用的五款蓝牙耳机推荐
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