如何在ISE中更新老版本的IP核
在ise中打开以前做的一个工程时，总是不停地提示
info:sim:760 - you can use the core generator ip upgrade flow to upgrade the selected ip block_memory_generator v3.1 to a more recent version.
老版本是ise11.1中生成的，现在用12.4了，推荐更新ip核。于是摸索了一下，找到了下面的步骤：
1. 在导航窗口中选择ip核生成的文件
2. 在core generator中双击manager core，如图所示
3. 点击出现的xilinx core generator窗口中，actions下面的update and regenerate……那一项即可，然后会出现提示：
welcome to xilinx core generator.
help system initialized.
opening project file d:\dul_ram\ipcore_dir\coregen.cgp.
info:sim:760 - you can use the core generator ip upgrade flow to upgrade the selected ip block_memory_generator v3.1 to a more recent version.
project, 'coregen', initialised from file 'd:\dul_ram\ipcore_dir\coregen.cgp'.
upgrade and regenerate all project ip (latest versions, under current project settings)
applying current project options...
finished applying current project options.
applying current project options...
finished applying current project options.
upgrading ip dul_ram to block memory generator version 4.3
launching upgrade viewer...
launched upgrade viewer.
initializing ip model...
finished initialising ip model.
generating ip...
warning:sim:89 - a core named already exists in the output directory. output products for this core may be overwritten.
initializing ip model...
warning:sim:602 - the parameter 'port_b_write_rate' is disabled and can't be set to any other value than '0'. its value will be reset from '50' to its last valid value '0'.
warning:sim:192 - xco parameter changed from (port_b_write_rate,50) to (port_b_write_rate,0) during recustomization.
finished initialising ip model.
xst: hdl compilation
xst: design hierarchy analysis
xst: hdl analysis
xst: hdl synthesis
xst: advanced hdl synthesis
xst: low level synthesis
generating implementation files.
generating ise symbol file...
warning:coreutil - warning: default charset gbk not supported, using iso-8859-1 instead
generating ngc file.
finished generation stage.
generating ip instantiation template...
vhdl instantiation template already present, so not regenerating.
warning:coreutil - warning: default charset gbk not supported, using iso-8859-1 instead
finished generating ip instantiation template.
generating metadata file...
finished generating metadata file.
generating ise file...
finished ise file generation.
generating flist file...
finished flist file generation.
preparing output directory...
finished preparing output directory.
info:sim - created backup directory d:\dul_ram\ipcore_dir\tmp\backup_dul_ram\
moving files to output directory...
finished moving files to output directory
saved options for project 'coregen'.
特斯拉发布自研自动驾驶芯片 14纳米三星代工取代英伟达产品
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info:sim:760 - you can use the core generator ip upgrade flow to upgrade the selected ip block_memory_generator v3.1 to a more recent version.
老版本是ise11.1中生成的，现在用12.4了，推荐更新ip核。于是摸索了一下，找到了下面的步骤：
1. 在导航窗口中选择ip核生成的文件
2. 在core generator中双击manager core，如图所示
3. 点击出现的xilinx core generator窗口中，actions下面的update and regenerate……那一项即可，然后会出现提示：
welcome to xilinx core generator.
help system initialized.
opening project file d:\dul_ram\ipcore_dir\coregen.cgp.
info:sim:760 - you can use the core generator ip upgrade flow to upgrade the selected ip block_memory_generator v3.1 to a more recent version.
project, 'coregen', initialised from file 'd:\dul_ram\ipcore_dir\coregen.cgp'.
upgrade and regenerate all project ip (latest versions, under current project settings)
applying current project options...
finished applying current project options.
applying current project options...
finished applying current project options.
upgrading ip dul_ram to block memory generator version 4.3
launching upgrade viewer...
launched upgrade viewer.
initializing ip model...
finished initialising ip model.
generating ip...
warning:sim:89 - a core named already exists in the output directory. output products for this core may be overwritten.
initializing ip model...
warning:sim:602 - the parameter 'port_b_write_rate' is disabled and can't be set to any other value than '0'. its value will be reset from '50' to its last valid value '0'.
warning:sim:192 - xco parameter changed from (port_b_write_rate,50) to (port_b_write_rate,0) during recustomization.
finished initialising ip model.
xst: hdl compilation
xst: design hierarchy analysis
xst: hdl analysis
xst: hdl synthesis
xst: advanced hdl synthesis
xst: low level synthesis
generating implementation files.
generating ise symbol file...
warning:coreutil - warning: default charset gbk not supported, using iso-8859-1 instead
generating ngc file.
finished generation stage.
generating ip instantiation template...
vhdl instantiation template already present, so not regenerating.
warning:coreutil - warning: default charset gbk not supported, using iso-8859-1 instead
finished generating ip instantiation template.
generating metadata file...
finished generating metadata file.
generating ise file...
finished ise file generation.
generating flist file...
finished flist file generation.
preparing output directory...
finished preparing output directory.
info:sim - created backup directory d:\dul_ram\ipcore_dir\tmp\backup_dul_ram\
moving files to output directory...
finished moving files to output directory
saved options for project 'coregen'.
特斯拉发布自研自动驾驶芯片 14纳米三星代工取代英伟达产品
PCB走线注意事项
常用电机控制电路图TOP12
控制电缆型号表示方法_控制电缆型号大全
北京全市累计开通的5G基站已经超过4.4万个
如何在ISE中更新老版本的IP核
MAX6581 精度、8通道温度传感器，有效降低电路板面积
详解模拟芯片内部的电路结构
无线物联网连接：如何选择无线技术
日本将为台积电熊本二厂提供高比例补贴
使用光纤收发器的注意事项
华为云CDN为什么这么受用户的信赖？
清明将至，假期出行绝佳搭档：华硕Mini PC PN50
如何判断传感器输出的是电流还是电压信号
江淮立足技术创新，加大汽车产业链布局
3G用户是如何访问外部数据网的？
鸿海赶工iPhone 15 苹链出货 旺季鸣枪
研究人员成功开发石墨烯/硅微米孔阵列异质结光探测器
广东移动5G网络建设和5G应用创新助力粤港澳大湾区打造了智慧城市群
高通或将面临平板和智能手机泡沫风险