Microprocessor Supervisors Off
abstract: discusses the value of a µp supervisor reset circuit in a microprocessor-based system. explains the terms associated with a supervisory circuit and how they should be implemented. subjects discussed include power-on reset (por), brownout conditions, and low-power failure. features discussed include manual reset input, power fail comparator, and watchdog timer.
battery backup circuits with chip enable gating feature also explored. in addition, the document discusses future requirements such as multi-voltage systems.
the world throws a wide range of problems at microprocessor-system designers. power supplies come up in the wrong sequence, ramp up too slowly, and stabilize too slowly. supply voltages glitch up and down due to external-component loads, or they drift in and out of tolerance as the bus voltages fluctuate or system batteries begin to fail. peripheral components and boards fail to power up and communicate in synchronization with the needs of the processor. and, in spite of lengthy pre-introduction software analysis, bugs sneak into the system code and are shipped to the field.
system designers do everything they can to minimize these events within a fixed-cost budget, but careful engineers want their system to operate safely even when a problem occurs. they want to ensure that the microprocessor-based system starts properly every time, that it detects when a system error has occurred or is about to occur, that it minimizes the effect of these errors, and that it returns safely from an error with little or no user intervention.
the modern microprocessor-supervisor circuit is a low-cost and effective method for monitoring and maintaining such system activity. applying techniques developed over the past several years, today's supervisors provide the insurance needed by microprocessor systems. they feature low power consumption, low cost, and a wide range of integrated functions in very small packages. power-on resetthe first and most commonly used safeguard for microprocessor systems is the power-on reset function. almost every computer and embedded processor includes a means for cold-starting the system, in the proper configuration, when power is first applied. most processor data sheets provide a minimum reset period, during which the device should remain out of operation until the local power supply has stabilized for a specified interval (200ms is typical). the processor is not guaranteed to operate correctly if brought out of reset too quickly. during this reset interval, the processor's clock is allowed to stabilize and the internal registers have time to load properly. most processor data sheets specify a minimum reset time, but they provide few guidelines for achieving this delay.
a common approach that is inexpensive but risky is to delay the reset signal using a resistor-capacitor low-pass filter at the microprocessor's reset-input pin (figure 1). you can select the component values to provide a wide range of reset delays based on a slow, exponential rc rise time. as the capacitor charges from ground to vcc, the voltage crosses a threshold recognized by the microprocessor as a valid (high) input voltage (vih). this action releases the processor from reset, and it should (ideally) begin normal operation. unfortunately, this approach has several drawbacks.
figure 1. resistor-capacitor reset delay circuit.
the first power-on problem is seen when the supply voltage rises slowly relative to the processor's reset time period. the capacitor voltage closely follows vcc for low slew rates. as a result, the reset input voltage at the processor can reach a valid vih level before vcc arrives within the tolerance range specified for the device. for a 3.3v supply with ±10% tolerance, for example, the reset should not de-assert until vcc > 2.97v. the system, however, can achieve a minimum vih level of 2.31v (0.7vcc for most processors) long before the supply is ready for processor operation. that is, the processor can be released from reset when the supply is still 20% or more below its nominal operating level.
a second shortfall of rc circuits is the lengthy reset-delay interval required for most processors (200ms typical), which compels a low rate of voltage slew at the processor's reset input. reset logic inputs are usually designed to recognize digital signals that make quick transitions from vil to vih. the delayed reset voltage, filtered to a slow µv/µs slew rate, can provide insufficient overdrive to the processor's digital input, a condition that results in reset metastability. a schmitt trigger between the rc filter and processor input can increase the apparent slew rate, but it can contribute power-up concerns of its own (besides additional cost and component area). brownout and glitch detectionbrownout detection, the second-most-common reset requirement, is closely related to power-on reset and highlights a third problem with the low-cost rc delay circuit. assuming the rc delay provides a reasonable interval for the processor to properly initialize before releasing the reset, the system is at risk if the supply voltage glitches or droops below its operating tolerance for any significant time interval.
because the rc circuit was selected to create a long rise-time delay on the reset signal, it filters out the relatively fast undervoltage glitches before the filtered reset signal can fall to vil. a fast negative glitch (relative to the reset delay time) can wreak havoc on the processor's internal registers, forcing it to execute wrong instructions, process incorrect data, or issue dangerous system signals. a supply droop, which can be sustained for a long period, can bring vcc below the processor's operating tolerance while maintaining the reset voltage above its reset-switching threshold.
an improved but still risky solution adds a diode to the rc circuit, thereby creating a fast filter response for large negative-going vcc signals (figure 2). as vcc drops below the charged capacitor voltage, the diode turns on and pulls the reset signal downward. this approach can be satisfactory for a hard drop of vcc, but a smaller drop (brownout) may not turn the diode on. for a 2.5v processor, for instance, the supply must drop more than 20% before the diode begins to discharge the capacitor voltage. if the glitch or droop is more than the processor tolerance but less than the diode's forward turn-on voltage, the processor's internal registers can be corrupted even though the supply recovers to its full vcc specification without triggering a processor reset.
figure 2. improved rc delay circuit. integrated reset generatorsproblems associated with rc delay circuits are easily solved by ic reset generators like the sot23 max6332-max6334 and the sc70 max809/max810/max803. by integrating an accurate voltage monitor with precise timing circuitry, these modern reset generators detect when the supply voltage is within the processor's tolerance and provide a guaranteed reset delay.
a typical reset device (figure 3) incorporates a voltage reference, a voltage comparator, a supply voltage resistor-divider network, a fixed-delay-time circuit, and an output driver stage. the resistor network can be adjusted at the factory for a wide range of supply-voltage tolerances, allowing the user to select a specific reset threshold for each processor application. the reset generator's accurate voltage detector, independent of its logic output stage, does not rely on the processor's high and low logic-input levels to determine when the supply is within its allowable operating tolerance.
figure 3. integrated reset circuit.
for power-on reset, the internal voltage comparator turns on the delay circuit only when the supply voltage exceeds the selected threshold for a sufficient period of time. delay generators, offering processor-compatible reset times ranging from 1ms to 1s, hold the output stage in reset until the minimum-specified period has expired. the generator output, available with several logic options, is then de-asserted to quickly drive the processor out of reset and into normal operation.
the voltage comparator in most reset generators also detects when the supply voltage drops back below the processor tolerance. if it drops below the selected threshold for sufficient time, the reset output quickly asserts its active-drive logic to suspend and re-initialize all processor activities. the reset can be activated at any time: a jagged startup of the power supply, large vcc glitches, brownout, or shutdown of the system. reset thresholdsa wide range of vcc reset thresholds are available in the industry today. many suppliers offer standard reset options for nominal supply voltages of 5v, 3.3v, 2.5v, and 1.8v. the customer can select a standard reset threshold to match a given nominal processor supply voltage and its minimum tolerance. reset tolerances are commonly available in processor-compatible options of -5% and -10%. for nonstandard reset voltages, some suppliers offer 100mv breaks over a wide vcc range of 1.6v to 5v, allowing users to optimize the threshold for specific combinations of component tolerance and supply voltage.
tighter accuracy for reset thresholds generally helps support looser and lower-cost power-supply specifications. for example, a system that guarantees operation for its 5v ±10% processor needs to initialize a reset before the supply drops to 4.5v. if the supervisor device has an accuracy of ±2.5%, guaranteed over temperature relative to the nominal vcc, the typical reset threshold is 4.625v and the maximum reset threshold is 4.75v. due to the supervisor's ±2.5% accuracy specification, the processor can reset for any vcc below 4.75v and is guaranteed to reset before vcc drops below 4.5v.
to support the supervisor accuracy overhead and avoid areas of unknown reset conditions, the resulting power supply should be specified for a tighter minimum limit (4.75v). the resulting 5v, -5%/+10% vcc specification could increase the power-supply cost substantially. thus, a more accurate ±1% or ±1.5% supervisor, though more expensive than ±2.5% devices, can actually lower the system cost.
an important function of the modern reset generator is to minimize nuisance resets: the undesired system restarts that occur when a short-duration small-magnitude spike depresses the supply voltage below its minimum-allowed level. to determine if a system reset is required, the voltage detector integrates glitch duration and intensity. a plot of the maximum supply-transient duration versus overdrive can illustrate how a reset generator responds to noise in the system supply (figure 4).
figure 4. maximum transient duration versus overdrive. manual resetan input for manual (pushbutton) reset is a useful addition to the simple reset generator. manual reset allows the user or an external system component to trigger a microprocessor reset while the supply voltage remains within tolerance. if the processor locks up for some unknown reason, the manual reset lets you start again without turning off the system power. this function is especially important for products that never power down the controlling processor, even in the off mode. it is also useful for debugging and for final system testing. in all cases, a manual reset can guarantee that the processor receives the necessary timeout period during reset.
manual resets are often initiated with a low-cost pushbutton switch, and reset devices like the max6335-max6337 series usually include input-debouncing circuitry to mask the effect of ringing initiated by contact closure in the grounded switch. because the switch can be remote to the processor (often on a back panel or hidden in a battery or power-supply compartment), the best manual-reset circuits accommodate long board runs by rejecting short (100ns typical) noise-induced pulses. to guarantee valid reset inputs (1µs typical), they also require a minimum input pulse width. the manual reset can be implemented as an independent input to the supervisor or as a dual-function pin that serves both as reset output and manual-reset input.
some microprocessors now integrate the power-on reset circuitry with their power-management functions. although these embedded reset circuits are usually better than the rc-delay approach, the µp ic process is optimized for high-speed or low-power digital performance rather than accurate and reliable analog measurement and timing. thus, internal resets can provide reasonable power-on timing under normal operating conditions, but they are poorly qualified to handle the supply transients and brownouts that can cause processor errors. for robust operation, most processors provide an additional reset input that can be driven by an external, dedicated reset supervisor. power-fail and low-battery indicatorsmany systems cannot afford to lose data even when the power supply drops out completely and the microprocessor fails. a hard reset resulting from loss of supply voltage causes the processor to dump any information held in its internal registers. a system can minimize this potential data loss by saving data continuously in a nonvolatile memory, but that approach reduces the processor efficiency and stresses the write endurance of flash or eeprom memories.
an improved method, implemented by the sot23-packaged max6342-max6345 supervisors, employs a power-fail or low-battery indicator that enables the processor to anticipate a loss of supply voltage. with advance warning, the processor can store information in nonvolatile memory before the system initiates a reset (figure 5).
figure 5. power-fail/low-battery indicator.
typical systems power the processor by regulating voltage from a primary supply or battery. this processor supply voltage is monitored by a standard power-on/brownout reset, but an independent low-voltage indicator also monitors the primary supply. the threshold for this indicator is set above the regulator dropout voltage, and its output drives a nonmaskable interrupt (nmi). this nmi instructs the processor to begin saving data into nonvolatile memory. if implemented properly, the low-voltage indicator provides sufficient time for storing all data before the regulated supply voltage drops below the processor's minimum operating specification. battery-backup and chip-enable gatingwhen a system lacks time to transfer large amounts of data to nonvolatile memory, battery backup is an attractive alternative. to accommodate dual supplies, devices such as the sot23 max6361/max6363/max6364 provide one input for the primary vcc and one for an onboard battery (figure 6).
figure 6. battery backup.
when the supply level is sufficient to maintain volatile ram activity, an internal switch connects the supervisor's voltage output to vcc. when vcc drops below a specified threshold, the supervisor disables further memory writes by issuing a reset to the microprocessor. if vcc drops too low to maintain the ram contents, the supervisor switches the ram supply from vcc to the backup battery. memory devices with low suspend current can hold data for very long periods, until the system vcc can be brought back to its proper operating level. if desired, the same battery-backup process can also sustain real-time clocks and certain processor activities. watchdog timereven the best-designed systems are subject to errors other than power-supply fluctuation. bad program code, incorrect clocking signals, or poorly responding peripherals can all force the processor out of its normal operating code or into a dead-end loop. when a processor leaves the expected instruction path, it may have no way of knowing that it is operating incorrectly and needs to restart.
to solve this problem, many supervisor ics (like the industry-standard max823 and newer max6316-max6318 devices) include a watchdog timer as a low-cost means for ensuring that the processor is executing within the proper code boundaries. this scheme requires that the processor update a watchdog logic input continually, within a specified minimum time period. otherwise, the supervisor issues a system alert (figure 7).
figure 7. watchdog timer option.
a common industry-standard timeout period for watchdogs is 1.6 seconds, but suppliers offer options from 1ms to 1 minute. because the watchdog update consumes processor-cycle overhead, you should select the watchdog period by asking how long can the system be allowed to operate incorrectly before a reset is initiated? some devices allow a longer startup timeout (1 minute, for example) before dropping back to the normal 1.6-second short-timeout operating mode. this dual-timeout capability allows the system to execute a lengthy boot process during startup and then become responsible for the faster, routine watchdog updates.
the watchdog output can at times be tied to a nonmaskable processor input, which lets the supervisor attempt to bring the processor back to normal operation without losing volatile memory data. to fully re-initialize the system on detection of any error, the watchdog can be tied in common with the power-on-reset/brownout-detect output.
many microprocessors now provide an internal watchdog timer to monitor their own internal state. because the watchdog is only a support feature for the processor, it usually offers a range of programmable timeout periods and disable options. the processor can also have the ability to modify its watchdog monitor function through software control. because the programmable watchdog operates from the same supply voltage and clock inputs as the processor, however, it is often subject to the same transient errors as the processor itself. thus, the most robust systems include an independent watchdog, which guarantees proper inputs to the processor each and every time. multiple-supply applicationsthe newer processors and many other systems require multiple-supply voltages. the trend toward multiple-supply devices is especially evident in high-speed small-geometry digital signal processors, which can communicate with a standard system i/o voltage of 3.3v but operate with core logic of 2.5v or lower. these devices often require that both supplies be within the processor's tolerance before the power-on reset is released. similarly, a complex receiver system can maintain four or five supply voltages (12v, 5v, -5v, 3.3v, and 2.5v, for example), which support a variety of analog and digital components. an undervoltage condition on any of these voltages can cause a system failure.
in spite of its low cost, a simple rc network cannot monitor multiple supplies simultaneously while providing a single valid logic level for the system reset. historically, manufacturers have created multiple-supply monitor circuits with multiple power-fail/reset detectors or by wiring the outputs of several single-supply reset devices in common. then, any supply voltage that sits below its specified tolerance holds off release of the processor reset.
some of the newer supervisors support multivoltage monitoring in single-package designs (figure 8). the max6351-max6360 family, designed for dual- and triple-supply applications, offers several options for factory-trimmed standard reset thresholds (that is, those associated with supply voltages of 3.3v and 2.5v, for example). an adjustable detector allows users to monitor a third supply voltage (as for a 5v analog peripheral) and hold off the processor start until all voltages are within tolerance. modern packages and processes allow maxim to squeeze extra functionality into the multivoltage sot23 reset supervisor, along with a watchdog timer of an extended start period and a manual-reset input.
figure 8. multiple-supply reset monitoring. the futureas processors demand greater performance from steadily shrinking integration processes, we should see lower operating voltages. if the current processor-supply tolerances of ±5% and ±10% remain unchanged, designers will demand even more accurate analog voltage detectors to replace their discrete-component alternatives. an older 5v-reset architecture that successfully monitors maximum supply deviations of -250mv may be incapable of supporting a new 1.2v monitor with a -60mv undervoltage limit. because many of these low-voltage systems will need to support a range of dual-supply devices and slower-changing legacy supply devices, the need for multivoltage monitoring to ensure proper operation should become more critical.
we should also witness the introduction of new integrations that combine supervisors with other components now surrounding the microprocessor. if an external chip provides power or communications for the processor, its integration offers an opportunity to shrink board area, cut power consumption, and reduce cost. a few of the functions being combined with supervisors today include low-dropout regulators, dc-dc converters, nonvolatile memory, and real-time clocks. conclusionthe best microprocessor supervisors are so designed and applied that the customer never knows they are in the system. such systems always power up properly, at no time lose or destroy data, and never lock up unexpectedly.
system designers appreciate the modern supervisor as a low-cost insurance policy that keeps the product working all the time. supervisors also improve the manufacturer's time to market, while minimizing field problems, customer service, and failure returns. because of the wide range of products now available in very small sot23 and sc70 packages, you can optimize an application requiring low power, low voltages, multiple-supply voltages, and low cost without sacrificing its functionality.
a similar article appeared in the november 2000 issue of sensors.
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battery backup circuits with chip enable gating feature also explored. in addition, the document discusses future requirements such as multi-voltage systems.
the world throws a wide range of problems at microprocessor-system designers. power supplies come up in the wrong sequence, ramp up too slowly, and stabilize too slowly. supply voltages glitch up and down due to external-component loads, or they drift in and out of tolerance as the bus voltages fluctuate or system batteries begin to fail. peripheral components and boards fail to power up and communicate in synchronization with the needs of the processor. and, in spite of lengthy pre-introduction software analysis, bugs sneak into the system code and are shipped to the field.
system designers do everything they can to minimize these events within a fixed-cost budget, but careful engineers want their system to operate safely even when a problem occurs. they want to ensure that the microprocessor-based system starts properly every time, that it detects when a system error has occurred or is about to occur, that it minimizes the effect of these errors, and that it returns safely from an error with little or no user intervention.
the modern microprocessor-supervisor circuit is a low-cost and effective method for monitoring and maintaining such system activity. applying techniques developed over the past several years, today's supervisors provide the insurance needed by microprocessor systems. they feature low power consumption, low cost, and a wide range of integrated functions in very small packages. power-on resetthe first and most commonly used safeguard for microprocessor systems is the power-on reset function. almost every computer and embedded processor includes a means for cold-starting the system, in the proper configuration, when power is first applied. most processor data sheets provide a minimum reset period, during which the device should remain out of operation until the local power supply has stabilized for a specified interval (200ms is typical). the processor is not guaranteed to operate correctly if brought out of reset too quickly. during this reset interval, the processor's clock is allowed to stabilize and the internal registers have time to load properly. most processor data sheets specify a minimum reset time, but they provide few guidelines for achieving this delay.
a common approach that is inexpensive but risky is to delay the reset signal using a resistor-capacitor low-pass filter at the microprocessor's reset-input pin (figure 1). you can select the component values to provide a wide range of reset delays based on a slow, exponential rc rise time. as the capacitor charges from ground to vcc, the voltage crosses a threshold recognized by the microprocessor as a valid (high) input voltage (vih). this action releases the processor from reset, and it should (ideally) begin normal operation. unfortunately, this approach has several drawbacks.
figure 1. resistor-capacitor reset delay circuit.
the first power-on problem is seen when the supply voltage rises slowly relative to the processor's reset time period. the capacitor voltage closely follows vcc for low slew rates. as a result, the reset input voltage at the processor can reach a valid vih level before vcc arrives within the tolerance range specified for the device. for a 3.3v supply with ±10% tolerance, for example, the reset should not de-assert until vcc > 2.97v. the system, however, can achieve a minimum vih level of 2.31v (0.7vcc for most processors) long before the supply is ready for processor operation. that is, the processor can be released from reset when the supply is still 20% or more below its nominal operating level.
a second shortfall of rc circuits is the lengthy reset-delay interval required for most processors (200ms typical), which compels a low rate of voltage slew at the processor's reset input. reset logic inputs are usually designed to recognize digital signals that make quick transitions from vil to vih. the delayed reset voltage, filtered to a slow µv/µs slew rate, can provide insufficient overdrive to the processor's digital input, a condition that results in reset metastability. a schmitt trigger between the rc filter and processor input can increase the apparent slew rate, but it can contribute power-up concerns of its own (besides additional cost and component area). brownout and glitch detectionbrownout detection, the second-most-common reset requirement, is closely related to power-on reset and highlights a third problem with the low-cost rc delay circuit. assuming the rc delay provides a reasonable interval for the processor to properly initialize before releasing the reset, the system is at risk if the supply voltage glitches or droops below its operating tolerance for any significant time interval.
because the rc circuit was selected to create a long rise-time delay on the reset signal, it filters out the relatively fast undervoltage glitches before the filtered reset signal can fall to vil. a fast negative glitch (relative to the reset delay time) can wreak havoc on the processor's internal registers, forcing it to execute wrong instructions, process incorrect data, or issue dangerous system signals. a supply droop, which can be sustained for a long period, can bring vcc below the processor's operating tolerance while maintaining the reset voltage above its reset-switching threshold.
an improved but still risky solution adds a diode to the rc circuit, thereby creating a fast filter response for large negative-going vcc signals (figure 2). as vcc drops below the charged capacitor voltage, the diode turns on and pulls the reset signal downward. this approach can be satisfactory for a hard drop of vcc, but a smaller drop (brownout) may not turn the diode on. for a 2.5v processor, for instance, the supply must drop more than 20% before the diode begins to discharge the capacitor voltage. if the glitch or droop is more than the processor tolerance but less than the diode's forward turn-on voltage, the processor's internal registers can be corrupted even though the supply recovers to its full vcc specification without triggering a processor reset.
figure 2. improved rc delay circuit. integrated reset generatorsproblems associated with rc delay circuits are easily solved by ic reset generators like the sot23 max6332-max6334 and the sc70 max809/max810/max803. by integrating an accurate voltage monitor with precise timing circuitry, these modern reset generators detect when the supply voltage is within the processor's tolerance and provide a guaranteed reset delay.
a typical reset device (figure 3) incorporates a voltage reference, a voltage comparator, a supply voltage resistor-divider network, a fixed-delay-time circuit, and an output driver stage. the resistor network can be adjusted at the factory for a wide range of supply-voltage tolerances, allowing the user to select a specific reset threshold for each processor application. the reset generator's accurate voltage detector, independent of its logic output stage, does not rely on the processor's high and low logic-input levels to determine when the supply is within its allowable operating tolerance.
figure 3. integrated reset circuit.
for power-on reset, the internal voltage comparator turns on the delay circuit only when the supply voltage exceeds the selected threshold for a sufficient period of time. delay generators, offering processor-compatible reset times ranging from 1ms to 1s, hold the output stage in reset until the minimum-specified period has expired. the generator output, available with several logic options, is then de-asserted to quickly drive the processor out of reset and into normal operation.
the voltage comparator in most reset generators also detects when the supply voltage drops back below the processor tolerance. if it drops below the selected threshold for sufficient time, the reset output quickly asserts its active-drive logic to suspend and re-initialize all processor activities. the reset can be activated at any time: a jagged startup of the power supply, large vcc glitches, brownout, or shutdown of the system. reset thresholdsa wide range of vcc reset thresholds are available in the industry today. many suppliers offer standard reset options for nominal supply voltages of 5v, 3.3v, 2.5v, and 1.8v. the customer can select a standard reset threshold to match a given nominal processor supply voltage and its minimum tolerance. reset tolerances are commonly available in processor-compatible options of -5% and -10%. for nonstandard reset voltages, some suppliers offer 100mv breaks over a wide vcc range of 1.6v to 5v, allowing users to optimize the threshold for specific combinations of component tolerance and supply voltage.
tighter accuracy for reset thresholds generally helps support looser and lower-cost power-supply specifications. for example, a system that guarantees operation for its 5v ±10% processor needs to initialize a reset before the supply drops to 4.5v. if the supervisor device has an accuracy of ±2.5%, guaranteed over temperature relative to the nominal vcc, the typical reset threshold is 4.625v and the maximum reset threshold is 4.75v. due to the supervisor's ±2.5% accuracy specification, the processor can reset for any vcc below 4.75v and is guaranteed to reset before vcc drops below 4.5v.
to support the supervisor accuracy overhead and avoid areas of unknown reset conditions, the resulting power supply should be specified for a tighter minimum limit (4.75v). the resulting 5v, -5%/+10% vcc specification could increase the power-supply cost substantially. thus, a more accurate ±1% or ±1.5% supervisor, though more expensive than ±2.5% devices, can actually lower the system cost.
an important function of the modern reset generator is to minimize nuisance resets: the undesired system restarts that occur when a short-duration small-magnitude spike depresses the supply voltage below its minimum-allowed level. to determine if a system reset is required, the voltage detector integrates glitch duration and intensity. a plot of the maximum supply-transient duration versus overdrive can illustrate how a reset generator responds to noise in the system supply (figure 4).
figure 4. maximum transient duration versus overdrive. manual resetan input for manual (pushbutton) reset is a useful addition to the simple reset generator. manual reset allows the user or an external system component to trigger a microprocessor reset while the supply voltage remains within tolerance. if the processor locks up for some unknown reason, the manual reset lets you start again without turning off the system power. this function is especially important for products that never power down the controlling processor, even in the off mode. it is also useful for debugging and for final system testing. in all cases, a manual reset can guarantee that the processor receives the necessary timeout period during reset.
manual resets are often initiated with a low-cost pushbutton switch, and reset devices like the max6335-max6337 series usually include input-debouncing circuitry to mask the effect of ringing initiated by contact closure in the grounded switch. because the switch can be remote to the processor (often on a back panel or hidden in a battery or power-supply compartment), the best manual-reset circuits accommodate long board runs by rejecting short (100ns typical) noise-induced pulses. to guarantee valid reset inputs (1µs typical), they also require a minimum input pulse width. the manual reset can be implemented as an independent input to the supervisor or as a dual-function pin that serves both as reset output and manual-reset input.
some microprocessors now integrate the power-on reset circuitry with their power-management functions. although these embedded reset circuits are usually better than the rc-delay approach, the µp ic process is optimized for high-speed or low-power digital performance rather than accurate and reliable analog measurement and timing. thus, internal resets can provide reasonable power-on timing under normal operating conditions, but they are poorly qualified to handle the supply transients and brownouts that can cause processor errors. for robust operation, most processors provide an additional reset input that can be driven by an external, dedicated reset supervisor. power-fail and low-battery indicatorsmany systems cannot afford to lose data even when the power supply drops out completely and the microprocessor fails. a hard reset resulting from loss of supply voltage causes the processor to dump any information held in its internal registers. a system can minimize this potential data loss by saving data continuously in a nonvolatile memory, but that approach reduces the processor efficiency and stresses the write endurance of flash or eeprom memories.
an improved method, implemented by the sot23-packaged max6342-max6345 supervisors, employs a power-fail or low-battery indicator that enables the processor to anticipate a loss of supply voltage. with advance warning, the processor can store information in nonvolatile memory before the system initiates a reset (figure 5).
figure 5. power-fail/low-battery indicator.
typical systems power the processor by regulating voltage from a primary supply or battery. this processor supply voltage is monitored by a standard power-on/brownout reset, but an independent low-voltage indicator also monitors the primary supply. the threshold for this indicator is set above the regulator dropout voltage, and its output drives a nonmaskable interrupt (nmi). this nmi instructs the processor to begin saving data into nonvolatile memory. if implemented properly, the low-voltage indicator provides sufficient time for storing all data before the regulated supply voltage drops below the processor's minimum operating specification. battery-backup and chip-enable gatingwhen a system lacks time to transfer large amounts of data to nonvolatile memory, battery backup is an attractive alternative. to accommodate dual supplies, devices such as the sot23 max6361/max6363/max6364 provide one input for the primary vcc and one for an onboard battery (figure 6).
figure 6. battery backup.
when the supply level is sufficient to maintain volatile ram activity, an internal switch connects the supervisor's voltage output to vcc. when vcc drops below a specified threshold, the supervisor disables further memory writes by issuing a reset to the microprocessor. if vcc drops too low to maintain the ram contents, the supervisor switches the ram supply from vcc to the backup battery. memory devices with low suspend current can hold data for very long periods, until the system vcc can be brought back to its proper operating level. if desired, the same battery-backup process can also sustain real-time clocks and certain processor activities. watchdog timereven the best-designed systems are subject to errors other than power-supply fluctuation. bad program code, incorrect clocking signals, or poorly responding peripherals can all force the processor out of its normal operating code or into a dead-end loop. when a processor leaves the expected instruction path, it may have no way of knowing that it is operating incorrectly and needs to restart.
to solve this problem, many supervisor ics (like the industry-standard max823 and newer max6316-max6318 devices) include a watchdog timer as a low-cost means for ensuring that the processor is executing within the proper code boundaries. this scheme requires that the processor update a watchdog logic input continually, within a specified minimum time period. otherwise, the supervisor issues a system alert (figure 7).
figure 7. watchdog timer option.
a common industry-standard timeout period for watchdogs is 1.6 seconds, but suppliers offer options from 1ms to 1 minute. because the watchdog update consumes processor-cycle overhead, you should select the watchdog period by asking how long can the system be allowed to operate incorrectly before a reset is initiated? some devices allow a longer startup timeout (1 minute, for example) before dropping back to the normal 1.6-second short-timeout operating mode. this dual-timeout capability allows the system to execute a lengthy boot process during startup and then become responsible for the faster, routine watchdog updates.
the watchdog output can at times be tied to a nonmaskable processor input, which lets the supervisor attempt to bring the processor back to normal operation without losing volatile memory data. to fully re-initialize the system on detection of any error, the watchdog can be tied in common with the power-on-reset/brownout-detect output.
many microprocessors now provide an internal watchdog timer to monitor their own internal state. because the watchdog is only a support feature for the processor, it usually offers a range of programmable timeout periods and disable options. the processor can also have the ability to modify its watchdog monitor function through software control. because the programmable watchdog operates from the same supply voltage and clock inputs as the processor, however, it is often subject to the same transient errors as the processor itself. thus, the most robust systems include an independent watchdog, which guarantees proper inputs to the processor each and every time. multiple-supply applicationsthe newer processors and many other systems require multiple-supply voltages. the trend toward multiple-supply devices is especially evident in high-speed small-geometry digital signal processors, which can communicate with a standard system i/o voltage of 3.3v but operate with core logic of 2.5v or lower. these devices often require that both supplies be within the processor's tolerance before the power-on reset is released. similarly, a complex receiver system can maintain four or five supply voltages (12v, 5v, -5v, 3.3v, and 2.5v, for example), which support a variety of analog and digital components. an undervoltage condition on any of these voltages can cause a system failure.
in spite of its low cost, a simple rc network cannot monitor multiple supplies simultaneously while providing a single valid logic level for the system reset. historically, manufacturers have created multiple-supply monitor circuits with multiple power-fail/reset detectors or by wiring the outputs of several single-supply reset devices in common. then, any supply voltage that sits below its specified tolerance holds off release of the processor reset.
some of the newer supervisors support multivoltage monitoring in single-package designs (figure 8). the max6351-max6360 family, designed for dual- and triple-supply applications, offers several options for factory-trimmed standard reset thresholds (that is, those associated with supply voltages of 3.3v and 2.5v, for example). an adjustable detector allows users to monitor a third supply voltage (as for a 5v analog peripheral) and hold off the processor start until all voltages are within tolerance. modern packages and processes allow maxim to squeeze extra functionality into the multivoltage sot23 reset supervisor, along with a watchdog timer of an extended start period and a manual-reset input.
figure 8. multiple-supply reset monitoring. the futureas processors demand greater performance from steadily shrinking integration processes, we should see lower operating voltages. if the current processor-supply tolerances of ±5% and ±10% remain unchanged, designers will demand even more accurate analog voltage detectors to replace their discrete-component alternatives. an older 5v-reset architecture that successfully monitors maximum supply deviations of -250mv may be incapable of supporting a new 1.2v monitor with a -60mv undervoltage limit. because many of these low-voltage systems will need to support a range of dual-supply devices and slower-changing legacy supply devices, the need for multivoltage monitoring to ensure proper operation should become more critical.
we should also witness the introduction of new integrations that combine supervisors with other components now surrounding the microprocessor. if an external chip provides power or communications for the processor, its integration offers an opportunity to shrink board area, cut power consumption, and reduce cost. a few of the functions being combined with supervisors today include low-dropout regulators, dc-dc converters, nonvolatile memory, and real-time clocks. conclusionthe best microprocessor supervisors are so designed and applied that the customer never knows they are in the system. such systems always power up properly, at no time lose or destroy data, and never lock up unexpectedly.
system designers appreciate the modern supervisor as a low-cost insurance policy that keeps the product working all the time. supervisors also improve the manufacturer's time to market, while minimizing field problems, customer service, and failure returns. because of the wide range of products now available in very small sot23 and sc70 packages, you can optimize an application requiring low power, low voltages, multiple-supply voltages, and low cost without sacrificing its functionality.
a similar article appeared in the november 2000 issue of sensors.
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