SPC563M64L7主要特性及框图_Discovery Plus开发板
st公司的spc563m64l7是用于汽车动力总成的32位power architecture mcu,是系统级芯片(soc),采用许多新特性的高性能90nm cmos技术,以降低成本和提高性能,power architecture®技术具有支持dsp的附加指令,以及诸如增强的时间处理单元,增强排队的模数转换器,控制局域网(can)和增强的模块输入/输出系统.此外,器件还集成了94kb sram和1.5mb闪存.本文介绍了spc563m64l7主要特性,框图,以及spc563mxx系列discovery plus开发板spc563m-disp主要特性和电路图,pcb顶层布局图.
these 32-bit automotive microcontrollers are a family of system-on-chip （soc） devices that contain many new features coupled with high performance 90 nm cmos technology to provide substantial reduction of cost per feature and significant performance improvement. the advanced and cost-efficient host processor core of this automotive controller family is built on power architecture® technology. this family contains enhancements that improve the architecture’s fit in embedded applications， includes additional instruction support for digital signal processing （dsp）， integrates technologies—such as an enhanced time processor unit， enhanced queued analog-to-digital converter， controller area network， and an enhanced modular input-output system—that are important for today’s lower-end powertrain applications. the device has a single level of memory hierarchy consisting of up to 94 kb on-chip sram and up to 1.5 mb of internal flash memory. the device also has an external bus interface （ebi） for ‘calibration’。
spc563m64l7主要特性：
single issue，32-bit power architecture® book e compliant e200z335 cpu core complex
– includes variable length encoding （vle） enhancements for code size reduction
32-channel direct memory access controller （dma）
interrupt controller （intc） capable of handling 364 selectable-priority interrupt sources： 191 peripheral interrupt sources， 8 software interrupts and 165 reserved interrupts.
frequency-modulated phase-locked loop （fmpll）
calibration external bus interface （ebi）（a）
system integration unit （siu）
up to 1.5 mbyte on-chip flash with flash controller
– fetch accelerator for single cycle flash access @80 mhz
up to 94 kbyte on-chip static ram （including up to 32 kbyte standby ram）
boot assist module （bam）
32-channel second-generation enhanced time processor unit （etpu）
– 32 standard etpu channels
– architectural enhancements to improve code efficiency and added flexibility
16-channels enhanced modular input-output system （emios）
enhanced queued analog-to-digital converter （eqadc）
decimation filter （part of eqadc）
silicon die temperature sensor
2 deserial serial peripheral interface （dspi） modules （compatible with microsecond bus）
2 enhanced serial communication interface （esci） modules compatible with lin
2 controller area network （flexcan） modules that support can 2.0b
nexus port controller （npc） per ieee-isto 5001-2003 standard
ieee 1149.1 （jtag） support nexus interface
on-chip voltage regulator controller that provides 1.2 v and 3.3 v internal supplies from a 5 v external source.
designed for lqfp144， and lqfp176
the spc563mxx series microcontrollers are system-on-chip devices that are built on power architecture® technology and：
are 100% user-mode compatible with the power architecture instruction set contain enhancements that improve the architecture’s fit in embedded applications
include additional instruction support for digital signal processing （dsp）
integrate technologies such as an enhanced time processor unit， enhanced queued analog-to-digital converter， controller area network， and an enhanced modular input-output system
operating parameters
– fully static operation， 0 mhz
– 80 mhz （plus 2% frequency modulation - 82 mhz）
– –40 c–150 c junction temperature operating range
– low power design
less than 400 mw power dissipation （nominal）
designed for dynamic power management of core and peripherals
software controlled clock gating of peripherals
low power stop mode， with all clocks stopped
– fabricated in 90 nm process
– 1.2 v internal logic
high performance e200z335 core processor
advanced microcontroller bus architecture （amba） crossbar switch （xbar）
enhanced direct memory access （edma） controller
interrupt controller （intc）
– 191 peripheral interrupt request sources， plus 165 reserved positions
– low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
frequency modulating phase-locked loop （fmpll）
calibration bus interface （ebi） （available only in the calibration package） system integration unit （siu） centralizes control of pads， gpio pins and external interrupts.
error correction status module （ecsm） provides configurable error-correcting codes （ecc） reporting
up to 1.5 mb on-chip flash memory
up to 94 kb on-chip static ram
boot assist module （bam） enables and manages the transition of mcu from reset to user code execution from internal flash memory， external memory on the calibration bus or download and execution of code via flexcan or esci.
periodic interrupt timer （pit）
– 32-bit wide down counter with automatic reload
– 4 channels clocked by system clock
– 1 channel clocked by crystal clock
system timer module （stm）
– 32-bit up counter with 8-bit prescaler
– clocked from system clock
– 4 channel timer compare hardware
software watchdog timer （swt） 32-bit timer
enhanced modular i/o system （emios）
– 16 standard timer channels （up to 14 channels connected to pins in lqfp144）
– 24-bit timer resolution
second-generation enhanced time processor unit （etpu2）
– high level assembler/compiler
– enhancements to make ‘c’ compiler more efficient
– new ‘engine relative’ addressing mode
enhanced queued a/d converter （eqadc）
– 2 independent on-chip rsd cyclic adcs
– up to 34 input channels available to the two on-chip adcs
– 4 pairs of differential analog input channels
2 deserial serial peripheral interface modules （dspi）
– spi provides full duplex communication ports with interrupt and dma request support
– deserial serial interface （dsi） achieves pin reduction by hardware serialization and deserialization of etpu， emios channels and gpio
2 enhanced serial communication interface （esci） modules
2 flexcan modules
nexus port controller （npc） per ieee-isto 5001-2003 standard ieee 1149.1 jtag controller （jtagc）
图1.spc563mxx系列框图
spc563mxx系列discovery plus开发板spc563m-disp
the spc563m-disp discovery kit helps you to discover spc56 m line power architecture® microcontrollers. the discovery board is based on spc563m64l7， a 32-bit power architecture book e compliant e200z335 cpu core with 1.5mbyte on-chip in an lqfp176 package. the numerous interfaces including can/sci/k-line/dspi/gpio make the spc56m-discovery an excellent starter kit for customer quick evaluation and project development. the spc56 m family is designed to address cost sensitive powertrain and transmission applications. the spc56 m line key functionality is time processing units （etpu） a coprocessor to create events in sync with internal or external signals without flooding the cpu with interrupt to serve.
图2.discovery plus开发板spc563m-disp外形图
图3.discovery plus开发板spc563m-disp硬件概述图
图4.discovery plus开发板spc563m-disp电路图
图5.discovery plus开发板spc563m-disp顶层pcb布局图
Murata BAC3S隔离式3W稳压单输出交流/直流转换器
首款针对物联网应用的CMOS图像传感器产品 — SC210IoT
为什么参数差的基准反而可能更好？
pcba方案设计——无线充气泵方案
阴阳师对光明大陆，你会选华为荣耀V9还是360N5
SPC563M64L7主要特性及框图_Discovery Plus开发板
直流12V转220V交流逆变器电路图 (500W)
从单品智能到智能物联 长虹推动智能化不断进步
PCB板焊盘不容易上锡的六个原因汇总
魅族Pro7销量惨败，魅族MX7救场何时发？魅族MX7高通芯片、全面屏设计、2500价格成标配
什么是大电流导电滑环，它的优势是什么
人工智能领域里绕不开的一大问题_人才缺口
谷歌下个月要发布的亲儿子手机和安卓8.0竟然有这么厉害的新功能？
浅谈FIFO设计思路
高性能有源防磁音箱的制作
CAN是什么意思？
虹软科技能否凭借视觉技术在智能车载占据鳌头
ARM与Synopsys扩大合作关系 达成ARM架构之SoC的功耗及效能之最佳化
诚迈科技与恩智浦半导体建立深度合作伙伴关系
新唐科技M484SGAAE控制器简介
these 32-bit automotive microcontrollers are a family of system-on-chip （soc） devices that contain many new features coupled with high performance 90 nm cmos technology to provide substantial reduction of cost per feature and significant performance improvement. the advanced and cost-efficient host processor core of this automotive controller family is built on power architecture® technology. this family contains enhancements that improve the architecture’s fit in embedded applications， includes additional instruction support for digital signal processing （dsp）， integrates technologies—such as an enhanced time processor unit， enhanced queued analog-to-digital converter， controller area network， and an enhanced modular input-output system—that are important for today’s lower-end powertrain applications. the device has a single level of memory hierarchy consisting of up to 94 kb on-chip sram and up to 1.5 mb of internal flash memory. the device also has an external bus interface （ebi） for ‘calibration’。
spc563m64l7主要特性：
single issue，32-bit power architecture® book e compliant e200z335 cpu core complex
– includes variable length encoding （vle） enhancements for code size reduction
32-channel direct memory access controller （dma）
interrupt controller （intc） capable of handling 364 selectable-priority interrupt sources： 191 peripheral interrupt sources， 8 software interrupts and 165 reserved interrupts.
frequency-modulated phase-locked loop （fmpll）
calibration external bus interface （ebi）（a）
system integration unit （siu）
up to 1.5 mbyte on-chip flash with flash controller
– fetch accelerator for single cycle flash access @80 mhz
up to 94 kbyte on-chip static ram （including up to 32 kbyte standby ram）
boot assist module （bam）
32-channel second-generation enhanced time processor unit （etpu）
– 32 standard etpu channels
– architectural enhancements to improve code efficiency and added flexibility
16-channels enhanced modular input-output system （emios）
enhanced queued analog-to-digital converter （eqadc）
decimation filter （part of eqadc）
silicon die temperature sensor
2 deserial serial peripheral interface （dspi） modules （compatible with microsecond bus）
2 enhanced serial communication interface （esci） modules compatible with lin
2 controller area network （flexcan） modules that support can 2.0b
nexus port controller （npc） per ieee-isto 5001-2003 standard
ieee 1149.1 （jtag） support nexus interface
on-chip voltage regulator controller that provides 1.2 v and 3.3 v internal supplies from a 5 v external source.
designed for lqfp144， and lqfp176
the spc563mxx series microcontrollers are system-on-chip devices that are built on power architecture® technology and：
are 100% user-mode compatible with the power architecture instruction set contain enhancements that improve the architecture’s fit in embedded applications
include additional instruction support for digital signal processing （dsp）
integrate technologies such as an enhanced time processor unit， enhanced queued analog-to-digital converter， controller area network， and an enhanced modular input-output system
operating parameters
– fully static operation， 0 mhz
– 80 mhz （plus 2% frequency modulation - 82 mhz）
– –40 c–150 c junction temperature operating range
– low power design
less than 400 mw power dissipation （nominal）
designed for dynamic power management of core and peripherals
software controlled clock gating of peripherals
low power stop mode， with all clocks stopped
– fabricated in 90 nm process
– 1.2 v internal logic
high performance e200z335 core processor
advanced microcontroller bus architecture （amba） crossbar switch （xbar）
enhanced direct memory access （edma） controller
interrupt controller （intc）
– 191 peripheral interrupt request sources， plus 165 reserved positions
– low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
frequency modulating phase-locked loop （fmpll）
calibration bus interface （ebi） （available only in the calibration package） system integration unit （siu） centralizes control of pads， gpio pins and external interrupts.
error correction status module （ecsm） provides configurable error-correcting codes （ecc） reporting
up to 1.5 mb on-chip flash memory
up to 94 kb on-chip static ram
boot assist module （bam） enables and manages the transition of mcu from reset to user code execution from internal flash memory， external memory on the calibration bus or download and execution of code via flexcan or esci.
periodic interrupt timer （pit）
– 32-bit wide down counter with automatic reload
– 4 channels clocked by system clock
– 1 channel clocked by crystal clock
system timer module （stm）
– 32-bit up counter with 8-bit prescaler
– clocked from system clock
– 4 channel timer compare hardware
software watchdog timer （swt） 32-bit timer
enhanced modular i/o system （emios）
– 16 standard timer channels （up to 14 channels connected to pins in lqfp144）
– 24-bit timer resolution
second-generation enhanced time processor unit （etpu2）
– high level assembler/compiler
– enhancements to make ‘c’ compiler more efficient
– new ‘engine relative’ addressing mode
enhanced queued a/d converter （eqadc）
– 2 independent on-chip rsd cyclic adcs
– up to 34 input channels available to the two on-chip adcs
– 4 pairs of differential analog input channels
2 deserial serial peripheral interface modules （dspi）
– spi provides full duplex communication ports with interrupt and dma request support
– deserial serial interface （dsi） achieves pin reduction by hardware serialization and deserialization of etpu， emios channels and gpio
2 enhanced serial communication interface （esci） modules
2 flexcan modules
nexus port controller （npc） per ieee-isto 5001-2003 standard ieee 1149.1 jtag controller （jtagc）
图1.spc563mxx系列框图
spc563mxx系列discovery plus开发板spc563m-disp
the spc563m-disp discovery kit helps you to discover spc56 m line power architecture® microcontrollers. the discovery board is based on spc563m64l7， a 32-bit power architecture book e compliant e200z335 cpu core with 1.5mbyte on-chip in an lqfp176 package. the numerous interfaces including can/sci/k-line/dspi/gpio make the spc56m-discovery an excellent starter kit for customer quick evaluation and project development. the spc56 m family is designed to address cost sensitive powertrain and transmission applications. the spc56 m line key functionality is time processing units （etpu） a coprocessor to create events in sync with internal or external signals without flooding the cpu with interrupt to serve.
图2.discovery plus开发板spc563m-disp外形图
图3.discovery plus开发板spc563m-disp硬件概述图
图4.discovery plus开发板spc563m-disp电路图
图5.discovery plus开发板spc563m-disp顶层pcb布局图
Murata BAC3S隔离式3W稳压单输出交流/直流转换器
首款针对物联网应用的CMOS图像传感器产品 — SC210IoT
为什么参数差的基准反而可能更好？
pcba方案设计——无线充气泵方案
阴阳师对光明大陆，你会选华为荣耀V9还是360N5
SPC563M64L7主要特性及框图_Discovery Plus开发板
直流12V转220V交流逆变器电路图 (500W)
从单品智能到智能物联 长虹推动智能化不断进步
PCB板焊盘不容易上锡的六个原因汇总
魅族Pro7销量惨败，魅族MX7救场何时发？魅族MX7高通芯片、全面屏设计、2500价格成标配
什么是大电流导电滑环，它的优势是什么
人工智能领域里绕不开的一大问题_人才缺口
谷歌下个月要发布的亲儿子手机和安卓8.0竟然有这么厉害的新功能？
浅谈FIFO设计思路
高性能有源防磁音箱的制作
CAN是什么意思？
虹软科技能否凭借视觉技术在智能车载占据鳌头
ARM与Synopsys扩大合作关系 达成ARM架构之SoC的功耗及效能之最佳化
诚迈科技与恩智浦半导体建立深度合作伙伴关系
新唐科技M484SGAAE控制器简介