基于PIC24FJ256DA210设计的16位MCU开发技术
pic24fj256da210 是microchip 公司的16位mcu，具有能和lcd显示器接口的图像控制器（gfx）模块，高达96kb的数据ram。pic24fj256da210高性能cpu采用改进型哈佛架构，32mhz时的性能高达16mips，内部振荡器8mhz，17位x17位单周期硬件乘法器，32位x16位硬件除发器。器件工作电压2.2v-3.6v，数字输入可达5.5v。主要用在消费类电子如电热控制，无绳电话，遥控单元，家用电器，销售终端（pos）以及手提医疗设如血糖仪，血压机，手提ecg等。本文介绍了pic24fj256da210系列主要特性，方框图和pic24fj256da210开发板主要特性，方框图以及详细电路图。
the pic24fj256da210 family enhances on the existing line of microchip‘s 16-bit microcontrollers, adding a new graphics controller (gfx) module to interface with a graphical lcd display and also adds large data ram, up to 96 kbytes. the pic24fj256da210 family allows the cpu to fetch data directly from an external memory device using the epmp module.
pic24fj256da210主要特性：
graphics controller features:
• three graphics hardware accelerators to facilitate rendering of block copying, text and unpacking of compressed data
• color look-up table (clut) with maximum of 256 entries
• 1/2/4/8/16 bits-per-pixel (bpp) color depth set at run time
• display resolution programmable according to frame buffer:
- supports direct access to external memory on devices with epmp
- resolution supported is up to 480x272 @ 60 hz, 16 bpp; 640x480 @ 30 hz, 16 bpp or 640x480 @ 60 hz, 8 bpp
• supports various display interfaces:
- 4/8/16-bit monochrome stn
- 4/8/16-bit color stn
- 9/12/18/24-bit color tft (18 and 24-bit displays are connected as 16-bit, 5-6-5 rgb color format)
universal serial bus features:
• usb v2.0 on-the-go (otg) compliant
• dual role capable – can act as either host or peripheral
• low-speed (1.5 mbps) and full-speed (12 mbps) usb operation in host mode
• full-speed usb operation in device mode
• high-precision pll for usb
• supports up to 32 endpoints (16 bidirectional):
- usb module can use the internal ram location from 0x800 to 0xffff as usb endpoint buffers
• on-chip usb transceiver with interface for off-chip transceiver
• supports control, interrupt, isochronous and bulk transfers
• on-chip pull-up and pull-down resistors
peripheral features:
• enhanced parallel master port/parallel slave port (epmp/psp), 100-pin devices only:
- direct access from cpu with an extended data space (eds) interface
- 4, 8 and 16-bit wide data bus
- up to 23 programmable address lines
- up to 2 chip select lines
- up to 2 acknowledgement lines (one per chip select)
- programmable address/data multiplexing
- programmable address and data wait states
- programmable polarity on control signals
• peripheral pin select:
- up to 44 available pins (100-pin devices)
• three 3-wire/4-wire spi modules (supports 4 frame modes)
• three i2c™ modules supporting multi-master/slave modes and 7-bit/10-bit addressing
• four uart modules:
- supports rs-485, rs-232, lin/j2602 protocols and irda®
• five 16-bit timers/counters with programmable prescaler
• nine 16-bit capture inputs, each with a dedicated time base
• nine 16-bit compare/pwm outputs, each with a dedicated time base
• hardware real-time clock and calendar (rtcc)
• enhanced programmable cyclic redundancy check (crc) generator
• up to 5 external interrupt sources
high-performance cpu
• modified harvard architecture
• up to 16 mips operation at 32 mhz
• 8 mhz internal oscillator
• 17-bit x 17-bit single-cycle hardware multiplier
• 32-bit by 16-bit hardware divider
• 16 x 16-bit working register array
• c compiler optimized instruction set architecture with flexible addressing modes
• linear program memory addressing, up to 12 mbytes
• data memory addressing, up to 16 mbytes:
- 2k sfr space
- 30k linear data memory
- 66k extended data memory
- remaining (from 16 mbytes) memory (external) can be accessed using extended data memory (eds) and epmp (eds is divided into 32-kbyte pages)
• two address generation units for separate read and write addressing of data memory
power management:
• on-chip voltage regulator of 1.8v
• switch between clock sources in real time
• idle, sleep and doze modes with fast wake-up and two-speed start-up
• run mode: 800 a/mips, 3.3v typical
• sleep mode current down to 20ua, 3.3v typical
• standby current with 32 khz oscillator: 22ua, 3.3v typical
analog features:
• 10-bit, up to 24-channel analog-to-digital (a/d) converter at 500 ksps:
- operation is possible in sleep mode
- band gap reference input feature
• three analog comparators with programmable input/output configuration
• charge time measurement unit (ctmu):
- supports capacitive touch sensing for touch screens and capacitive switches
- minimum time measurement setting at 100 ps
• available lvd interrupt vlvd level
special microcontroller features:
• operating voltage range of 2.2v to 3.6v
• 5.5v tolerant input (digital pins only)
• configurable open-drain outputs on digital i/o ports
• high-current sink/source (18 ma/18 ma) on all i/o ports
• selectable power management modes:
- sleep, idle and doze modes with fast wake-up
• fail-safe clock monitor (fscm) operation:
- detects clock failure and switches to on-chip, frc oscillator
• on-chip ldo regulator
• power-on reset (por) and oscillator start-up timer (ost)
• brown-out reset (bor)
• flexible watchdog timer (wdt) with on-chip low-power rc oscillator for reliable operation
• in-circuit serial programming™ (icsp™) and in-circuit debug (icd) via 2 pins
• jtag boundary scan support
• flash program memory:
- 10,000 erase/write cycle endurance (minimum)
- 20-year data retention minimum
- selectable write protection boundary
- self-reprogrammable under software control
- write protection option for configuration words
图1。pic24fj256da210系列方框图
pic24fj256da210开发板
the pic24fj256da210 development board is an efficient, low-cost development platform报to evaluate the features and performance of microchip’s pic24fj256da210 microcontroller. the 16-bit microcontroller integrates a high-performance graphics controller, ctmu and usb otg modules essential for integrated human interface applications.
supporting this is a range of user-defined interfaces, usb options and memory expansions for the maximum flexibility in developing graphics-capable solutions. a range of microchip development tools and software environments, along with a range of application libraries, simplifies the process of software development.
topics discussed in this chapter include:
• development board features
• power requirements
• companion display panels
• typical development board configurations
• development board demonstration programs
• additional software for application development
图2。pic24fj256da210开发板外形图
图3。pic24fj256da210开发板方框图
图3。pic24fj256da210开发板电路图（mcu）
图4。pic24fj256da210开发板电路图（开关，电位计和触摸点）
图5。pic24fj256da210开发板电路图（闪存和sram选择）
图6。pic24fj256da210开发板电路图（usb和uart选择，电源）
图7。pic24fj256da210开发板电路图（显示连接器icd和pickit连接器）
图8。pic24fj256da210开发板电路图（pictail™ plus 连接器和pictail配置选择）
图9。pic24fj256da210开发板电路图（mcu插座）
纳微半导体发生新人事任命
区块链技术开发市场的新玩家
新技术新方法，消费级的量子计算机离我们又近了一步
鲲鹏GCC编译器具有代表性的三方面优化特性
美国无人系统 无人机服务市场大有所为
基于PIC24FJ256DA210设计的16位MCU开发技术
Laird Connectivity的Lyra系列蓝牙5.3模块和Littelfuse 的汽车级保险丝EV1K系列
河套IT TALK96：（原创）GPT技术揭秘：解锁提示工程的潜能
百度AI的发展如何
无人驾驶的汽车内饰该是什么样的？
在应用编程MAXQ微控制器中可分区擦除的程序和数据闪存
FPGA上的HBM性能实测结果分析
米尔参加openEuler大会，助力国产工业控制器软硬件升级
精简ISA扩展总线接口读写操作
传言2021年微软会对Surface Pro的工业设计进行大手术？
Silicon Labs推出Bluetooth网状网络解决方案
苏泊尔物联网净水机DR3H6成为家庭净水优选
人工智能在未来不会取代人类只会让人更智能
IR推出可靠的AUIR3320S智能电源开关
AMD 7纳米CPU/GPU明年1月发布 英特尔10纳米或遭降级
the pic24fj256da210 family enhances on the existing line of microchip‘s 16-bit microcontrollers, adding a new graphics controller (gfx) module to interface with a graphical lcd display and also adds large data ram, up to 96 kbytes. the pic24fj256da210 family allows the cpu to fetch data directly from an external memory device using the epmp module.
pic24fj256da210主要特性：
graphics controller features:
• three graphics hardware accelerators to facilitate rendering of block copying, text and unpacking of compressed data
• color look-up table (clut) with maximum of 256 entries
• 1/2/4/8/16 bits-per-pixel (bpp) color depth set at run time
• display resolution programmable according to frame buffer:
- supports direct access to external memory on devices with epmp
- resolution supported is up to 480x272 @ 60 hz, 16 bpp; 640x480 @ 30 hz, 16 bpp or 640x480 @ 60 hz, 8 bpp
• supports various display interfaces:
- 4/8/16-bit monochrome stn
- 4/8/16-bit color stn
- 9/12/18/24-bit color tft (18 and 24-bit displays are connected as 16-bit, 5-6-5 rgb color format)
universal serial bus features:
• usb v2.0 on-the-go (otg) compliant
• dual role capable – can act as either host or peripheral
• low-speed (1.5 mbps) and full-speed (12 mbps) usb operation in host mode
• full-speed usb operation in device mode
• high-precision pll for usb
• supports up to 32 endpoints (16 bidirectional):
- usb module can use the internal ram location from 0x800 to 0xffff as usb endpoint buffers
• on-chip usb transceiver with interface for off-chip transceiver
• supports control, interrupt, isochronous and bulk transfers
• on-chip pull-up and pull-down resistors
peripheral features:
• enhanced parallel master port/parallel slave port (epmp/psp), 100-pin devices only:
- direct access from cpu with an extended data space (eds) interface
- 4, 8 and 16-bit wide data bus
- up to 23 programmable address lines
- up to 2 chip select lines
- up to 2 acknowledgement lines (one per chip select)
- programmable address/data multiplexing
- programmable address and data wait states
- programmable polarity on control signals
• peripheral pin select:
- up to 44 available pins (100-pin devices)
• three 3-wire/4-wire spi modules (supports 4 frame modes)
• three i2c™ modules supporting multi-master/slave modes and 7-bit/10-bit addressing
• four uart modules:
- supports rs-485, rs-232, lin/j2602 protocols and irda®
• five 16-bit timers/counters with programmable prescaler
• nine 16-bit capture inputs, each with a dedicated time base
• nine 16-bit compare/pwm outputs, each with a dedicated time base
• hardware real-time clock and calendar (rtcc)
• enhanced programmable cyclic redundancy check (crc) generator
• up to 5 external interrupt sources
high-performance cpu
• modified harvard architecture
• up to 16 mips operation at 32 mhz
• 8 mhz internal oscillator
• 17-bit x 17-bit single-cycle hardware multiplier
• 32-bit by 16-bit hardware divider
• 16 x 16-bit working register array
• c compiler optimized instruction set architecture with flexible addressing modes
• linear program memory addressing, up to 12 mbytes
• data memory addressing, up to 16 mbytes:
- 2k sfr space
- 30k linear data memory
- 66k extended data memory
- remaining (from 16 mbytes) memory (external) can be accessed using extended data memory (eds) and epmp (eds is divided into 32-kbyte pages)
• two address generation units for separate read and write addressing of data memory
power management:
• on-chip voltage regulator of 1.8v
• switch between clock sources in real time
• idle, sleep and doze modes with fast wake-up and two-speed start-up
• run mode: 800 a/mips, 3.3v typical
• sleep mode current down to 20ua, 3.3v typical
• standby current with 32 khz oscillator: 22ua, 3.3v typical
analog features:
• 10-bit, up to 24-channel analog-to-digital (a/d) converter at 500 ksps:
- operation is possible in sleep mode
- band gap reference input feature
• three analog comparators with programmable input/output configuration
• charge time measurement unit (ctmu):
- supports capacitive touch sensing for touch screens and capacitive switches
- minimum time measurement setting at 100 ps
• available lvd interrupt vlvd level
special microcontroller features:
• operating voltage range of 2.2v to 3.6v
• 5.5v tolerant input (digital pins only)
• configurable open-drain outputs on digital i/o ports
• high-current sink/source (18 ma/18 ma) on all i/o ports
• selectable power management modes:
- sleep, idle and doze modes with fast wake-up
• fail-safe clock monitor (fscm) operation:
- detects clock failure and switches to on-chip, frc oscillator
• on-chip ldo regulator
• power-on reset (por) and oscillator start-up timer (ost)
• brown-out reset (bor)
• flexible watchdog timer (wdt) with on-chip low-power rc oscillator for reliable operation
• in-circuit serial programming™ (icsp™) and in-circuit debug (icd) via 2 pins
• jtag boundary scan support
• flash program memory:
- 10,000 erase/write cycle endurance (minimum)
- 20-year data retention minimum
- selectable write protection boundary
- self-reprogrammable under software control
- write protection option for configuration words
图1。pic24fj256da210系列方框图
pic24fj256da210开发板
the pic24fj256da210 development board is an efficient, low-cost development platform报to evaluate the features and performance of microchip’s pic24fj256da210 microcontroller. the 16-bit microcontroller integrates a high-performance graphics controller, ctmu and usb otg modules essential for integrated human interface applications.
supporting this is a range of user-defined interfaces, usb options and memory expansions for the maximum flexibility in developing graphics-capable solutions. a range of microchip development tools and software environments, along with a range of application libraries, simplifies the process of software development.
topics discussed in this chapter include:
• development board features
• power requirements
• companion display panels
• typical development board configurations
• development board demonstration programs
• additional software for application development
图2。pic24fj256da210开发板外形图
图3。pic24fj256da210开发板方框图
图3。pic24fj256da210开发板电路图（mcu）
图4。pic24fj256da210开发板电路图（开关，电位计和触摸点）
图5。pic24fj256da210开发板电路图（闪存和sram选择）
图6。pic24fj256da210开发板电路图（usb和uart选择，电源）
图7。pic24fj256da210开发板电路图（显示连接器icd和pickit连接器）
图8。pic24fj256da210开发板电路图（pictail™ plus 连接器和pictail配置选择）
图9。pic24fj256da210开发板电路图（mcu插座）
纳微半导体发生新人事任命
区块链技术开发市场的新玩家
新技术新方法，消费级的量子计算机离我们又近了一步
鲲鹏GCC编译器具有代表性的三方面优化特性
美国无人系统 无人机服务市场大有所为
基于PIC24FJ256DA210设计的16位MCU开发技术
Laird Connectivity的Lyra系列蓝牙5.3模块和Littelfuse 的汽车级保险丝EV1K系列
河套IT TALK96：（原创）GPT技术揭秘：解锁提示工程的潜能
百度AI的发展如何
无人驾驶的汽车内饰该是什么样的？
在应用编程MAXQ微控制器中可分区擦除的程序和数据闪存
FPGA上的HBM性能实测结果分析
米尔参加openEuler大会，助力国产工业控制器软硬件升级
精简ISA扩展总线接口读写操作
传言2021年微软会对Surface Pro的工业设计进行大手术？
Silicon Labs推出Bluetooth网状网络解决方案
苏泊尔物联网净水机DR3H6成为家庭净水优选
人工智能在未来不会取代人类只会让人更智能
IR推出可靠的AUIR3320S智能电源开关
AMD 7纳米CPU/GPU明年1月发布 英特尔10纳米或遭降级