基于CS42L37设计的低功耗音频CODEC技术
本文介绍了cs42l37主要特性,方框图, 典型连接框图以及cs42l37评估板主要特性, 评估系统方框图以及评估板详细电路图与智能音频codec应用框图.
cs42l37是cirrus公司的高度集成的低功耗音频和电话codec,主要用于手持应用如智能手机和超小型移动计算机. cs42l37具有灵活的时钟架构,时钟频率有6, 12, 24, 13, 26, 19.2, 或38.4 mhz,具有立体声adc,支持双路模拟或数字mic,双路mic偏压发生器,4个dac耦合到5个输出. 立体声adc动态范围91db,thd+n为-85db,2:1立体声模拟输入复接器, 立体声dac到线路输出动态翻番97db,thd+n为-86db,h类放大器.
the cs42l73 is a highly integrated, low-power, audio and telephony codec for portable applications such as smartphones and ultra mobile personal computers.
the cs42l73 features a flexible clocking architecture, allowing the device to utilize reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 mhz, or any standard audio master clock. up to two reference/master clock sources may be connected; either one can be selected to drive the internal clocks and processing rate of the cs42l73.
thus, multiple master clock sources within a system can be dynamically activated and de-activated to minimize system-level power consumption.
three asynchronous bidirectional serial ports (auxiliary, audio, and voice serial ports) support multiple clock domains of various digital audio sources or destinations. three low-latency, fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the cs42l73.
a stereo line input or two mono (one stereo) microphone (mic) inputs are routed to a stereo adc. the mic inputs may be selectively pre-amplified by +10 or +20 db. two independent, low-noise mic bias voltage supplies are also provided. a programmable gain amplifier (pga) is applied to the inputs before they reach the adc.
the stereo input path that follows the stereo adc begins with a multiplexer to selectively choose data from a digital mic interface. following the multiplexer, the data is decimated, selectively dc high-pass filtered, channelswapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. the volume levels can be automatically adjusted via a programmable automatic level control (alc) and noise gate.
a digital mixer is utilized to mix and route the cs42l73’s inputs (analog inputs to adc, digital mic, or serial ports) to outputs (dac-fed amplifiers or serial ports). there is independent attenuation on each mixer input for each output.
the processing along the output paths from the digital mixer to the two stereo dacs includes volume adjustment and mute control. a peak-detector can be used to automatically adjust the volume levels via a programmable limiter.
the first stereo dac feeds the stereo headphone and line output amplifiers, which are powered from a dedicated positive supply. an integrated charge pump provides a negative supply. this allows a ground-centered analog output with a wide signal swing, and eliminates external dc-blocking capacitors while reducing pops and clicks. trilevel class-h amplification is utilized to reduce power consumption under low-signal-level conditions. analog volume controls are provided on the stereo headphone and line outputs.
the second stereo dac feeds several mono outputs. the left channel of the dac sources a mono, differentialdrive, speakerphone amplifier for driving the handset speakerphone. the right channel sources a mono, differential- drive, earphone amplifier for driving the handset earphone. the right channel is also routed to a mono,differential-drive, speakerphone line output, which may be connected to an external amplifier to implement a stereo speakerphone configuration when it is used in conjunction with the integrated speakerphone amplifier.
the cs42l73 implements robust power management to achieve ultra-low power consumption. high granularity in power-down controls allows individual functional blocks to be powered down when unused. the internal low dropout regulator (ldo) saves power by running the internal digital circuits at half the logic interface supply voltage (vl/2). in a system with an existing high-efficiency supply at vl/2, the internal ldo may be disabled and the digital circuits powered directly by the external vl/2 supply.
a high-speed i²c control port interface capable of up to 400 khz operation facilitates register programming.
the cs42l73 is available in space-saving 64-ball wlcsp and 65-ball fbga packages for the commercial (-40° to +85℃) grade.
cs42l37主要特性:
product overview
stereo adc
dual analog or digital mic support
dual mic bias generators
four dacs coupled to five outputs
ground-centered stereo headphone amp.
– ground-centered stereo line output
– mono ear speaker amplifier
– mono 1 w speakerphone amplifier
– mono speakerphone line output for stereo speakerphone expansion
three serial ports with asynchronous sample rate converters
digital audio mixing and routing
ultra low power consumption
3.5 mw quiescent headphone playback
cs42l37应用:
smart phones, umpcs, and mids
system features
native (no pll required) support for 6/12/24 mhz, 13/26 mhz, and 19.2/38.4 mhz master clock rates in add. to typ. audio clock rates
integrated high-efficiency power management reduces power consumption
– internal ldo regulator to reduce internal digital operating voltage to vl/2
step-down charge pump provides low headphone/line out supply voltage
– inverting charge pump accommodates low system voltage by providing negative rail
for hp and line amp
flexible speakerphone amplifier powering
– 3.00 v to 5.25 v range
– independent cycling
power down management
– individual controls for adcs, dig. mic interface, mic bias generators, serial ports, and output amplifiers & associated dacs
programmable thermal overload notification
high-speed i²c™ control port (400 khz)
stereo analog to digital features
91 db dynamic range (a-wtd)
-85 db thd+n
independent adc channel control
2:1 stereo analog input mux
stereo line input
– shared pseudo-differential reference input
dual analog mic inputs
– pseudo-diff. or single-ended
– two, independent, programmable, lownoise, mic bias outputs
– mic short detect to support headset button
analog programmable gain amplifier (pga) (+12 to -6 db in 0.5 db steps)
+10 db or +20 db analog mic boost in addition to pga gain settings
programmable automatic level control (alc)
– noise gate for noise suppression
– progr. threshold & attack/release rates
dual digital microphone interface
programable clock rate
– integer divide by 2 or 4 of internal mclk
stereo dac to headphone amplifier
94 db dynamic range (a-wtd)
-81 db thd+n into 32
integrated step-down/inverting charge pump
class h amplifier - automatic supply adj.
– high efficiency
– low emi
pseudo-differential ground-centered outputs
high hp power output at -70/-81 db thd+n
– 2 x 17/8.5 mw into 16/32 @ 1.8 v
pop and click suppression
analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans.
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
stereo dac to line outputs
97 db dynamic range (a-wtd)
-86 db thd+n
class-h amplifier
pseudo-differential ground-centered outputs
1 vrms line output @ 1.8 v
pop and click suppression
analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans.
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to ear speaker amplifier
high power output at -70 db (0.032%) thd+n
– 45 mw into 16@ 1.8 v
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to speakerphone amplifier
high output power at ≤1% thd+n
– 1.18/0.84/0.66 w into 8@ 5.0/4.2/3.7 v
direct battery-powered operation
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to speakerph. line output
84 db dynamic range (a-wtd)
-75 db thd+n
high voltage (1.53 vrms @ va = 1.8 v, vp =3.7 v) line output to ensure maximum output from a wide variety of external amplifiers
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
serial ports
three independent serial ports: auxiliary, audio, and voice
8.00, 11.025, 12.00, 16.00, 22.05, 24.00, 32.00, 44.10, and 48.00 khz sample rates
all ports support master or slave operation with i²s interface
auxiliary and voice ports support slave operation with pcm interface
auxiliary and audio ports are stereo-input/stereo-output to/from digital mixer
voice port is mono-input/stereo-output to/from digital mixer
integrated asynch. sample rate converters
图1.cs42l37方框图
图2.cs42l37典型连接框图
cs42l37评估板
the cdb42l73 board is a dedicated platform for testing and evaluating the cs42l73, an ultralow power mobile audio and telephony codec.
to allow comprehensive testing of cs42l73 features and performance, extensive hardware and software configurable options are available on the cdb42l73.
hardware options, such as power-supply settings, are configured via jumpers on the stake headers. software options, such as registry settings for the cs42l73, are configured with the flexgui software, which communicates with the cdb42l73 via usb from a windows® compatible computer. in addition, digital i/o headers on the cdb42l73 allow external control signals (for example, an external dsp or microcontroller) to configure and interface with the cs42l73 and other devices directly without the use of flexgui.
the cdb42l73 also serves as a good component and layout reference for the cs42l73.
cs42l37评估板主要特性:
analog inputs
– line-level in via 2x mono rca jacks
– microphone in via 2x mono 1/8” jacks
analog outputs
– headphone out via 1x stereo 1/8” jack
– line-level out via 2x mono rca jacks
– earphone out via terminal block
– speakerphone out via terminal blocks
s/pdif interface via rca/optical jacks
– input: cs8416 digital audio receiver
– output: cs8406 digital audio transmitter
external digital i/o via stake headers
– digital mic in
– serial audio port i/o
– external i²c™ control port i/o
flexible power-supply configuration
– usb, external power supply, or battery
flexgui software control
– windows® compatible
– predefined and user-configurable scripts
图3.cs42l37评估板外形图
图4.cs42l37评估系统方框图
图5.cs42l37评估板电路图:cs42l73
图6.cs42l37评估板电路图:usb和mcu
图7.cs42l37评估板电路图:s/pdif接收器,发送器,时钟缓冲器
图8.cs42l37评估板电路图:电源
图9.cs42l37智能音频codec应用框图
三星电子推出新款图像传感器ISOCELL 缩短中端智能手机开发周期有望
脉冲信号怎么产生
SKYLAB：带PA、传输距离更远的蓝牙网关TD05A
雷柏新款键盘来袭，颜值与实力皆在线不容错过
国务委员兼外长王毅表示华为是百分之百的民营企业
基于CS42L37设计的低功耗音频CODEC技术
多家手机厂商抱团： 担心苹果垄断OLED供应
低功耗WiFi模块，让智能穿戴更便捷
LG手机国内销量惨淡，G6或不在中国发售
迪比科推出一款USB PD四口桌面充电器，满足一充四
中国汽车经销商巨正通汽车深陷资金链危机
LED显示屏的安装方法有哪些
oppor11天猫搜索摇摇领先，是什么让它这么火？
纳芯微为中央空调应用提供全面的传感器解决方案
经纬仪打开对中激光的方法
可恒定控制多台电热箱温度的控制器电路图
数字货币交易所搭建，虚拟币交易平台网站开发商
中国广电5G网络的发展趋势分析
甲醛传感器模块ZE08-CH2O简介
新一代多旋翼工业级无人机迎来重大突破
cs42l37是cirrus公司的高度集成的低功耗音频和电话codec,主要用于手持应用如智能手机和超小型移动计算机. cs42l37具有灵活的时钟架构,时钟频率有6, 12, 24, 13, 26, 19.2, 或38.4 mhz,具有立体声adc,支持双路模拟或数字mic,双路mic偏压发生器,4个dac耦合到5个输出. 立体声adc动态范围91db,thd+n为-85db,2:1立体声模拟输入复接器, 立体声dac到线路输出动态翻番97db,thd+n为-86db,h类放大器.
the cs42l73 is a highly integrated, low-power, audio and telephony codec for portable applications such as smartphones and ultra mobile personal computers.
the cs42l73 features a flexible clocking architecture, allowing the device to utilize reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 mhz, or any standard audio master clock. up to two reference/master clock sources may be connected; either one can be selected to drive the internal clocks and processing rate of the cs42l73.
thus, multiple master clock sources within a system can be dynamically activated and de-activated to minimize system-level power consumption.
three asynchronous bidirectional serial ports (auxiliary, audio, and voice serial ports) support multiple clock domains of various digital audio sources or destinations. three low-latency, fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the cs42l73.
a stereo line input or two mono (one stereo) microphone (mic) inputs are routed to a stereo adc. the mic inputs may be selectively pre-amplified by +10 or +20 db. two independent, low-noise mic bias voltage supplies are also provided. a programmable gain amplifier (pga) is applied to the inputs before they reach the adc.
the stereo input path that follows the stereo adc begins with a multiplexer to selectively choose data from a digital mic interface. following the multiplexer, the data is decimated, selectively dc high-pass filtered, channelswapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. the volume levels can be automatically adjusted via a programmable automatic level control (alc) and noise gate.
a digital mixer is utilized to mix and route the cs42l73’s inputs (analog inputs to adc, digital mic, or serial ports) to outputs (dac-fed amplifiers or serial ports). there is independent attenuation on each mixer input for each output.
the processing along the output paths from the digital mixer to the two stereo dacs includes volume adjustment and mute control. a peak-detector can be used to automatically adjust the volume levels via a programmable limiter.
the first stereo dac feeds the stereo headphone and line output amplifiers, which are powered from a dedicated positive supply. an integrated charge pump provides a negative supply. this allows a ground-centered analog output with a wide signal swing, and eliminates external dc-blocking capacitors while reducing pops and clicks. trilevel class-h amplification is utilized to reduce power consumption under low-signal-level conditions. analog volume controls are provided on the stereo headphone and line outputs.
the second stereo dac feeds several mono outputs. the left channel of the dac sources a mono, differentialdrive, speakerphone amplifier for driving the handset speakerphone. the right channel sources a mono, differential- drive, earphone amplifier for driving the handset earphone. the right channel is also routed to a mono,differential-drive, speakerphone line output, which may be connected to an external amplifier to implement a stereo speakerphone configuration when it is used in conjunction with the integrated speakerphone amplifier.
the cs42l73 implements robust power management to achieve ultra-low power consumption. high granularity in power-down controls allows individual functional blocks to be powered down when unused. the internal low dropout regulator (ldo) saves power by running the internal digital circuits at half the logic interface supply voltage (vl/2). in a system with an existing high-efficiency supply at vl/2, the internal ldo may be disabled and the digital circuits powered directly by the external vl/2 supply.
a high-speed i²c control port interface capable of up to 400 khz operation facilitates register programming.
the cs42l73 is available in space-saving 64-ball wlcsp and 65-ball fbga packages for the commercial (-40° to +85℃) grade.
cs42l37主要特性:
product overview
stereo adc
dual analog or digital mic support
dual mic bias generators
four dacs coupled to five outputs
ground-centered stereo headphone amp.
– ground-centered stereo line output
– mono ear speaker amplifier
– mono 1 w speakerphone amplifier
– mono speakerphone line output for stereo speakerphone expansion
three serial ports with asynchronous sample rate converters
digital audio mixing and routing
ultra low power consumption
3.5 mw quiescent headphone playback
cs42l37应用:
smart phones, umpcs, and mids
system features
native (no pll required) support for 6/12/24 mhz, 13/26 mhz, and 19.2/38.4 mhz master clock rates in add. to typ. audio clock rates
integrated high-efficiency power management reduces power consumption
– internal ldo regulator to reduce internal digital operating voltage to vl/2
step-down charge pump provides low headphone/line out supply voltage
– inverting charge pump accommodates low system voltage by providing negative rail
for hp and line amp
flexible speakerphone amplifier powering
– 3.00 v to 5.25 v range
– independent cycling
power down management
– individual controls for adcs, dig. mic interface, mic bias generators, serial ports, and output amplifiers & associated dacs
programmable thermal overload notification
high-speed i²c™ control port (400 khz)
stereo analog to digital features
91 db dynamic range (a-wtd)
-85 db thd+n
independent adc channel control
2:1 stereo analog input mux
stereo line input
– shared pseudo-differential reference input
dual analog mic inputs
– pseudo-diff. or single-ended
– two, independent, programmable, lownoise, mic bias outputs
– mic short detect to support headset button
analog programmable gain amplifier (pga) (+12 to -6 db in 0.5 db steps)
+10 db or +20 db analog mic boost in addition to pga gain settings
programmable automatic level control (alc)
– noise gate for noise suppression
– progr. threshold & attack/release rates
dual digital microphone interface
programable clock rate
– integer divide by 2 or 4 of internal mclk
stereo dac to headphone amplifier
94 db dynamic range (a-wtd)
-81 db thd+n into 32
integrated step-down/inverting charge pump
class h amplifier - automatic supply adj.
– high efficiency
– low emi
pseudo-differential ground-centered outputs
high hp power output at -70/-81 db thd+n
– 2 x 17/8.5 mw into 16/32 @ 1.8 v
pop and click suppression
analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans.
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
stereo dac to line outputs
97 db dynamic range (a-wtd)
-86 db thd+n
class-h amplifier
pseudo-differential ground-centered outputs
1 vrms line output @ 1.8 v
pop and click suppression
analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans.
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to ear speaker amplifier
high power output at -70 db (0.032%) thd+n
– 45 mw into 16@ 1.8 v
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to speakerphone amplifier
high output power at ≤1% thd+n
– 1.18/0.84/0.66 w into 8@ 5.0/4.2/3.7 v
direct battery-powered operation
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
mono dac to speakerph. line output
84 db dynamic range (a-wtd)
-75 db thd+n
high voltage (1.53 vrms @ va = 1.8 v, vp =3.7 v) line output to ensure maximum output from a wide variety of external amplifiers
pop and click suppression
digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions
programmable peak-detect and limiter
serial ports
three independent serial ports: auxiliary, audio, and voice
8.00, 11.025, 12.00, 16.00, 22.05, 24.00, 32.00, 44.10, and 48.00 khz sample rates
all ports support master or slave operation with i²s interface
auxiliary and voice ports support slave operation with pcm interface
auxiliary and audio ports are stereo-input/stereo-output to/from digital mixer
voice port is mono-input/stereo-output to/from digital mixer
integrated asynch. sample rate converters
图1.cs42l37方框图
图2.cs42l37典型连接框图
cs42l37评估板
the cdb42l73 board is a dedicated platform for testing and evaluating the cs42l73, an ultralow power mobile audio and telephony codec.
to allow comprehensive testing of cs42l73 features and performance, extensive hardware and software configurable options are available on the cdb42l73.
hardware options, such as power-supply settings, are configured via jumpers on the stake headers. software options, such as registry settings for the cs42l73, are configured with the flexgui software, which communicates with the cdb42l73 via usb from a windows® compatible computer. in addition, digital i/o headers on the cdb42l73 allow external control signals (for example, an external dsp or microcontroller) to configure and interface with the cs42l73 and other devices directly without the use of flexgui.
the cdb42l73 also serves as a good component and layout reference for the cs42l73.
cs42l37评估板主要特性:
analog inputs
– line-level in via 2x mono rca jacks
– microphone in via 2x mono 1/8” jacks
analog outputs
– headphone out via 1x stereo 1/8” jack
– line-level out via 2x mono rca jacks
– earphone out via terminal block
– speakerphone out via terminal blocks
s/pdif interface via rca/optical jacks
– input: cs8416 digital audio receiver
– output: cs8406 digital audio transmitter
external digital i/o via stake headers
– digital mic in
– serial audio port i/o
– external i²c™ control port i/o
flexible power-supply configuration
– usb, external power supply, or battery
flexgui software control
– windows® compatible
– predefined and user-configurable scripts
图3.cs42l37评估板外形图
图4.cs42l37评估系统方框图
图5.cs42l37评估板电路图:cs42l73
图6.cs42l37评估板电路图:usb和mcu
图7.cs42l37评估板电路图:s/pdif接收器,发送器,时钟缓冲器
图8.cs42l37评估板电路图:电源
图9.cs42l37智能音频codec应用框图
三星电子推出新款图像传感器ISOCELL 缩短中端智能手机开发周期有望
脉冲信号怎么产生
SKYLAB：带PA、传输距离更远的蓝牙网关TD05A
雷柏新款键盘来袭，颜值与实力皆在线不容错过
国务委员兼外长王毅表示华为是百分之百的民营企业
基于CS42L37设计的低功耗音频CODEC技术
多家手机厂商抱团： 担心苹果垄断OLED供应
低功耗WiFi模块，让智能穿戴更便捷
LG手机国内销量惨淡，G6或不在中国发售
迪比科推出一款USB PD四口桌面充电器，满足一充四
中国汽车经销商巨正通汽车深陷资金链危机
LED显示屏的安装方法有哪些
oppor11天猫搜索摇摇领先，是什么让它这么火？
纳芯微为中央空调应用提供全面的传感器解决方案
经纬仪打开对中激光的方法
可恒定控制多台电热箱温度的控制器电路图
数字货币交易所搭建，虚拟币交易平台网站开发商
中国广电5G网络的发展趋势分析
甲醛传感器模块ZE08-CH2O简介
新一代多旋翼工业级无人机迎来重大突破